Intermediate Verilog Questions for Designers (Part – 2) : Strengthen Your Coding and Design Skills

1. What is the difference between synthesis and simulation?

• Simulation: The process of verifying the behavior of a Verilog design using software tools before hardware implementation.
• Synthesis: The process of converting Verilog code into a gate-level netlist or hardware description that can be physically implemented.

2. How to prevent race conditions in simulations?

• Use non-blocking assignments (<=) for sequential logic like flip-flops to ensure all right-hand side expressions are evaluated before any left-hand side updates, enabling simultaneous output updates and avoiding unintended ordering dependencies.
• Maintain proper sensitivity lists in always blocks so the logic triggers only on relevant signal changes, preventing unnecessary or missed evaluations that could cause simulation inconsistencies.
• Avoid mixing blocking (=) and non-blocking (<=) assignments within the same always block, as this can lead to simulation mismatches and unpredictable ordering effects that cause race conditions.
• Use synchronous resets whenever possible, and if asynchronous resets are needed, implement proper reset synchronization circuits to prevent metastability and timing hazards that contribute to race conditions.
• Structure your design hierarchically and modularly to ensure clear and well-defined data flow, minimizing combinational feedback loops that can cause races.
• Perform thorough timing verification and static timing analysis to detect and fix potential race conditions caused by clock skew, signal propagation delays, or setup/hold violations before hardware implementation.

3. Difference between ifdef and ifndef?

• ifdef (If Defined) checks whether a specific macro or symbol has been defined earlier in the code or via compiler options. If the macro is defined, the code block following ifdef is included in the compilation; otherwise, it is skipped.
• ifndef (If Not Defined) does the opposite: it checks if the macro is not defined. If the macro is not defined, the code block following ifndef is included; otherwise, it is skipped.

Example of ifdef:

`define DEBUG

`ifdef DEBUG
    initial begin
        $display("Debug mode is enabled.");
    end
`endif

• Here, since DEBUG is defined, the message "Debug mode is enabled." will be printed during simulation.
• If DEBUG was not defined, the entire block inside ifdef would be ignored.

Example of ifndef:

`ifndef SYNTHESIS
    initial begin
        $display("This code runs only during simulation, not synthesis.");
    end
`endif

• This block will be included only if the macro SYNTHESIS is not defined.
• Typically, designers define SYNTHESIS during synthesis runs to exclude simulation-only code.

ifdef and ifndef directives help control conditional compilation, enabling flexible and reusable code for different environments such as simulation, synthesis, debugging, or different target platforms.

4. What is the purpose of the disable statement in Verilog?

The disable statement in Verilog is used to prematurely terminate the execution of a named block, task, or fork-join process before it naturally completes. This allows you to exit from loops, blocks, or tasks based on certain conditions, improving control flow within your design or testbench.

• It works by specifying the label of the block or task you want to terminate.
• When disable is executed, the named block immediately stops executing, and control passes to the statement following that block.
• It is particularly useful in procedural blocks where you want to abort execution under specific conditions, especially in testbenches and complex behavioral models.

Example of disable with Named Block:

module disable_example;
  reg [3:0] count;
  
  initial begin : counting_block
    count = 0;
    forever begin
      #5 count = count + 1;
      $display("Count = %d", count);
      if (count == 5) begin
        disable counting_block;  // Terminate the named block prematurely
      end
    end
    $display("Counting stopped.");
  end
endmodule

Explanation

• The initial block is labeled as counting_block.
• Inside the block, a forever loop increments and displays the value of count every 5 time units.
• When count reaches 5, the disable counting_block; statement is executed.
• This immediately terminates the entire counting_block, stopping the loop and skipping any further statements inside it.
• The message "Counting stopped." is never printed because it is inside the disabled block after the loop.

5. How do you implement a shift register in Verilog?

A shift register is a sequential circuit that shifts its stored data by one position on every clock cycle, typically used for data storage, serialization, or delay.

always @(posedge clk) begin
    shift_reg <= {shift_reg[N-2:0], data_in};
end

• This code models an N-bit shift register, where shift_reg is an N-bit register and data_in is a single-bit input that enters the register on each clock cycle.
•  It shifts all bits to the left by one position and inserting data_in at the least significant bit.

6. What is the role of fork-join in Verilog?

• The fork-join construct allows multiple procedural statements or blocks to execute concurrently (in parallel) within a single process. This is particularly useful in testbenches and simulation environments where you want to model parallel activities such as multiple stimulus generators or simultaneous event monitoring.
• When the simulator encounters a fork statement, it spawns all the statements inside the block to run at the same simulation time, independently of each other.
• The join statement causes the parent process to wait until all the parallel statements inside the fork block have completed before proceeding further. This synchronization ensures that subsequent code executes only after all parallel tasks finish.
• Without fork-join, Verilog executes procedural statements sequentially, so fork-join is essential for modeling true concurrency in simulation.

Simple Example:

initial begin
    fork
        // Task 1: Wait 5 time units and display message
        #5 $display("Task 1 completed at time %0t", $time);

        // Task 2: Wait 10 time units and display message
        #10 $display("Task 2 completed at time %0t", $time);
    join
    $display("Both tasks completed at time %0t", $time);
end

Explanation:

• Both tasks start simultaneously at time 0.
• Task 1 completes at time 5, Task 2 at time 10.
• The final message prints only after both tasks have finished, i.e., at time 10.

7. Implement an up counter in Verilog.

always @(posedge clk) 
    count <= count + 1;

• The above code implements a binary up-counter that continuously counts upward, wrapping around upon reaching its maximum value depending on the bit-width of count.
• Such counters are widely used for introducing delay, event counting, or generating periodic signals in digital designs.

8. Implement a modulo counter in Verilog.

A modulo counter is a digital counter that counts from 0 up to a specified maximum value (modulus – 1), then wraps around back to 0 and repeats. The modulus defines the number of unique states the counter cycles through. For example, A mod-8 counter counts from 0 to 7, then resets to 0. Modulo counter is useful in timers, frequency dividers, and  digital clocks.

Verilog Implementation of a Parameterized Modulo Counter:

module modulo_counter #(
    parameter WIDTH = 4,         // Number of bits
    parameter MODULUS = 10       // Modulus value (max count + 1)
)(
    input wire clk,
    input wire rst_n,
    output reg [WIDTH-1:0] count
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count <= 0;
    end else begin
        if (count == MODULUS - 1) begin
            count <= 0;  // Wrap around
        end else begin
            count <= count + 1;
        end
    end
end

endmodule

9. Implement a ring counter in Verilog.

A ring counter is a type of shift register where a single logic ‘1’ (or ‘high’ bit) circulates through the register bits in a circular fashion. It is a simple sequential circuit used for counting, sequencing, or generating timing signals.

Verilog Code:

module ring_counter (
    input wire clk,
    input wire rst_n,
    output reg [7:0] q
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        // Initialize with a single '1' at the MSB (or LSB, your choice)
        q <= 8'b10000000;  
    end else begin
        // Rotate bits right by 1: move q[0] to q[7], shift others right
        q <= {q[0], q[7:1]};
    end
end

endmodule

10. Implement a Johnson counter in Verilog

A Johnson counter is a type of shift register where the inverted output of the last flip-flop is fed back as the input to the first flip-flop. This creates a unique sequence of bit patterns cycling through twice the number of states compared to a simple ring counter.

For an n-bit Johnson counter:

• The counter cycles through 2n unique states.
• The output pattern forms a “walking” sequence of ones and zeros.
• It is widely used in digital timing, sequencing, and waveform generation.

Example: 4-bit Johnson Counter Sequence

Verilog code of a n-bit Johnson counter:

module johnson_counter_nbit #(
    parameter N = 8
)(
    input wire clk,
    input wire rst_n,
    output reg [N-1:0] q
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        q <= {N{1'b0}};  // Initialize to zero
    end else begin
        q <= {q[N-2:0], ~q[N-1]};
    end
end

endmodule