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FPGA stands for Field Programmable Gate Array. They are programmable integrated circuits made up of a large number configurable logic blocks (CLBs), fixed function blocks and memory blocks which can be used to perform complex digital computations. The CLBs are the basic and most important unit of FPGA. CLBs are made up of Look Up…
There are two basic types of digital design methodologies: top-down Design Methodology In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided. bottom-up Design Methodology…
“There is Plenty of Room at the Bottom“ A popular talk delivered by Richard Feynman to American Physical Society at California Institute of Technology in the year of 1959. This talk at that time could foresee the possibility of the revolution which has been brought by VLSI today. The term VLSI stands for Very Large…
Port mapping in module instantiation can be done in two different ways: In this post, we would take one example to understand both types of port mapping in detail. The above Figure shows an example for module instantiation. Figure shows module “SYNCHRO” which consists of 2 ‘D’ flip-flops and are connected in serial fashion. Module “SYNCHRO”…
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A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. Each…
Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All ports declared as one of the above is assumed to be a wire by default,…
A “module” is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. Module interface refers, how module communicates with external world. This communication…
The states which are equivalent, are redundant. Because by looking at the output, we can not even figure out in which state the machine is in. So, if there are two equivalent states then there is no point of using both the states. We can merge both the states and can use only one state….
Sometimes a state diagram constructed for a finite state machine contains redundant states, i.e. states whose function can be accomplished by other states. The number of memory elements required for the realization of a machine is directly related to the number of states. Consequently, the minimization of the number of states does reduce the complexity…
This post illustrates the circuit design of Even Parity Generator. State Machine diagram for the same Parity Generator has been shown below. Click here to realize how we reach to the following state transition diagram. Click here to learn the step by step procedure of “How to synthesize a state machine / How to boil down…