Let's Program the Transistors
Qualcomm Interview Question Bank continued from Part 2… Q : What is the difference between latch and flip-flop? A : The main differences between latch and flip-flop can be understood here. Q : What is the Nyquist rate condition and condition for no aliasing to take place? A : If a signal is bandlimited to W…
Qualcomm Interview Question Bank continued from Part 1… Q : Draw the circuit diagram for a random number generator. A : Following are the circuits for a random number generator (RNG), (i) using IC 555 timer, IC 4026 and 7-segment, (ii) using 8051 and 7-segment, Q : What are the advantages and disadvantage of IIR and…
In the campus placement season, it is better if we get company specific questions to prepare for the selection process. So, to help you out, we have already posted Question Banks for some core ECE companies and now, let us look at the following questions asked in recent times in Qualcomm interviews. In general, according…
The TLM 2.0 transaction level modeling standard from the Open SystemC Initiative (OSCI) was released on 9th June 2008. Transaction-level modeling (TLM) is a high-level modern approach to modeling digital systems. That modeling is based on the abstraction of the communications between different parts of the model to allow to work the algorithms of each…
Read More “Getting started with TLM 2.0 – Introduction and Basic Constructs” »
Transaction-level modeling (TLM) is a high-level modern approach for modeling digital systems. TLM-1 standard defined a set of interfaces which could be used for transporting transaction by value or reference. TLM-1 is being used successfully in some applications but it had shortcomings which have now been improved upon in TLM 2.0. TLM-1 has no standard…
Read More “What is TLM-1 and what was the need for TLM 2.0?” »
Texas Instruments Question Bank continued from Part 1 Q. Draw 2:1 Mux using pass transistors. Ans: Two pass transistors are required to design 2:1 Mux. Q. Draw 2:1 Mux using transmission gates. Ans: Two transmission gates are required to design 2:1 Mux. Q. What is setup and hold time? Ans: Setup time is the minimum amount of time that an input signal…
Q. Implement a 3 bit asynchronous counter using T flip flops. Ans: To design 3 bit asynchronous counter we require 3 T flip flops. Q. What is the always block used for in Verilog? Ans: An always blocks runs continuously throughout the simulation. An always block can be made sensitive to one or more signals depending on the…
Bharat Electronics Limited (BEL) Question Bank continued from Part 4… Q-29. If the gain of the amplifier is A and voltage feedback is fraction B of the amplifier output voltage, what will be the condition for maintenance of oscillation? A : The condition for maintenance of oscillation would be AB = 1. Q-30. State the condition…
Read More “Bharat Electronics Limited (BEL) Question Bank – Part 5” »
The Synopsys University Program announces the 2016 student design contest in India featuring Synopsys Custom Design tools. This contest gives students the opportunity to showcase their talent in electronic design. Teams selected to compete in the contest will receive a free 3-day training workshop hosted by Synopsys and the chance to win a cash prize….
Bharat Electronics Limited (BEL) Question Bank continued from Part 3… Q-20. State a way to improve SNR at the input of an amplifier. A : Signal to Noise Ratio (SNR) at the input of an amplifier can be improved by decreasing the source impedance (or resistance). Q-21. Why are N channel FETs superior to P channel…
Read More “Bharat Electronics Limited (BEL) Question Bank – Part 4” »