Intermediate Verilog Questions for Designers (Part – 1) : Strengthen Your Coding and Design Skills

1. Model a tri-state buffer in Verilog.

assign out = enable ? data : 1'bz;

• When enable is high (1), the output out drives the value of data.
• When enable is low (0), the output out goes to high-impedance state (Z), effectively disconnecting from the line.

2. Implement a 2-to-1 multiplexer in Verilog using a continuous assignment.

assign y = sel ? a : b;

• When sel is 1 (true), the output y takes the value of input a.
• When sel is 0 (false), the output y takes the value of input b.

3. Model a combinational circuit using case?

always @(*) 
    case (sel)
        2'b00: y = a;
        2'b01: y = b; 
        default: y = 0; 
    endcase

• The always @(*) block defines a combinational logic block that automatically reacts to any changes in its input signals, ensuring the output updates immediately without clock dependency.
• Inside the block, the case statement selects the output y based on the value of the selector signal sel.
  • When sel is 2'b00, y is assigned the value of input a.
  • When sel is 2'b01, y is assigned the value of input b.
  • For all other values of sel (handled by default), y is assigned 0.
• This structure effectively models a multiplexer-like combinational circuit, where the output depends on the selector inputs.

4. How do you model a flip-flop in Verilog?

A flip-flop is edge sensitive. The following code represents a positive-edge-triggered D flip-flop that stores the value of d at each rising clock edge.

always @(posedge clk) begin
    q <= d;
end

• The flip-flop is modeled using an always block triggered on the positive edge of the clock (posedge clk), ensuring data is captured only at clock transitions.
• Inside the block, a non-blocking assignment (<=) updates the output q with the input d, modeling the storage behavior of the flip-flop.

5. How do you model a latch in Verilog?

A latch is level-sensitive and can be modeled using an always block sensitive to the enable signal.

always @(enable or d) begin
    if (enable)
        q = d;
end

Notice that the latch design uses a blocking assignment and the flip-flop design (Question 4) uses a non-blocking assignment.

• In the latch code, a blocking assignment (=) is used because latches are level-sensitive and the output q must update immediately and sequentially within the procedural block as the inputs change, accurately modeling the transparent behavior during the enable signal.
• In the flip-flop code, a non-blocking assignment (<=) is used to ensure that all flip-flops in a synchronous design update their outputs simultaneously at the clock edge, preventing race conditions and ensuring correct timing and simulation behavior in sequential logic.

6. How do you model an asynchronous reset flip-flop in Verilog?

always @(posedge clk or posedge reset) begin
    if (reset)
        q <= 0;
    else
        q <= d;
end

• The always block is triggered on either the positive edge of the clock (posedge clk) or the positive edge of the reset signal (posedge reset).
• This means the flip-flop responds immediately to the reset signal, regardless of the clock.
• When reset goes high, the flip-flop output q is asynchronously set to 0 immediately, without waiting for the clock edge.
• If reset is not asserted, the flip-flop captures the input d at the rising edge of the clock.
• The reset is asynchronous because it can override the flip-flop output at any time, independent of the clock.
• This is useful for quickly initializing or clearing the flip-flop state.
• However, asynchronous reset may lead to glitches on the output of the flip-flop.

7. How do you model a synchronous reset flip-flop in Verilog?

always @(posedge clk) begin
    if (reset)
        q <= 0;
    else
        q <= d;
end

• The always block is triggered only on the positive edge of the clock (posedge clk).
• Inside the block, the reset condition is checked.
• If reset is asserted (high) at the clock edge, the output q is reset to 0.
• Otherwise, the flip-flop captures the input d.
• This ensures the reset happens synchronously with the clock signal, and avoids glitches.

8. Implement a parity generator in Verilog?

A parity generator creates a parity bit for error detection by checking the number of 1s in input data bits. Using the XOR operation across all input bits efficiently produces the parity.

Verilog Code Snippet for Parity Generator:

module parity_generator (
    input  [7:0] data,
    output       parity  // odd parity bit
);

    assign parity = ^data;  // XOR reduction operator

endmodule

• The XOR reduction operator (^) computes the parity bit by XOR-ing all input bits.
• The output is 1 if the number of 1s in the input is odd (odd parity).
• For even parity, invert the XOR result.
• This approach is efficient and commonly used in hardware design for parity generation.

Check out Circuit Design of Parity Generator and Parity Code for Error Detection

9. What is the difference between case, casex, and casez?

• case: Matches the case expression exactly, including x and z bits.
• casex: Treats both x (unknown) and z (high-impedance) bits in the case expression and case items as don’t-care, allowing flexible matching.
• casez: Treats only z bits as don’t-care, while x bits are treated as normal bits.

Example:

module case_examples;
    reg [1:0] sel;
    reg [1:0] val;

    initial begin
        sel = 2'b1x;  // 'x' in LSB

        // case example (exact match)
        case (sel)
            2'b10: val = 1;  // No match because sel has 'x'
            2'b1x: val = 2;  // Syntax error: 'case' does not allow x in case item
            default: val = 0;
        endcase
        $display("case val = %d", val); // Prints case val = 0

        // casex example (x and z are don't-care)
        casex (sel)
            2'b10: val = 1;  // Matches because 'x' is ignored
            default: val = 0;
        endcase
        $display("casex val = %d", val); // Prints case val = 1

        // casez example (only z is don't-care)
        casez (sel)
            2'b1z: val = 1;  // Does not match because sel has 'x' not 'z'
            default: val = 0;
        endcase
        $display("casez val = %d", val); // Prints case val = 0
    end
endmodule

Explanation of the output:

• In the case block, since sel contains an x, no exact match occurs, so val is set to 0.
• In the casex block, the x in sel is treated as don’t-care, so 2'b10 matches 2'b1x and val is set to 1.
• In the casez block, only z is treated as don’t-care, so 2'b1z does not match 2'b1x, and val remains 0.

This demonstrates how casex is the most permissive (ignoring both x and z), casez ignores only z, and case requires exact matches including unknown bits.

10. Model a clock signal in testbench.

initial begin 
    clk = 0; 
    forever #5 clk = ~clk; 
end

• The initial block runs once at the start of the simulation to initialize and generate the clock signal.
• clk = 0; initializes the clock signal to a low logic level at time zero.
• The forever loop continuously toggles the clock signal by inverting (~clk) its value every 5 time units using the delay #5.
• This creates a periodic clock waveform with a total period of 10 time units (5 units low + 5 units high), simulating a clock signal for driving synchronous circuits during simulation.