Basic Verilog Questions for Beginners (Part – 1) : Build Your Foundations

1. What is Verilog and why is it used in VLSI design?

Verilog is a Hardware Description Language (HDL) widely used to design and model digital electronic systems. It helps in writing structured, reusable code to describe how a circuit should function. Verilog is crucial in VLSI design because it supports simulation, verification, and hardware synthesis, making the design-to-silicon process faster and more efficient.

2. What are the different levels of abstraction in Verilog?

There are 4 levels of abstraction in Verilog:

• Behavioral level: Describes what the system does using high-level constructs without specifying how it is implemented.
• Dataflow level: Describes how data flows between registers and through combinational logic.
• Gate level: Describes the circuit as a collection of logic gates and their interconnections.
• Switch level: Describes the circuit in terms of transistors and their connections.

3. How do you declare a module in Verilog?

A module is declared using the module and endmodule keywords. Below is an example:

module half_adder(input a, input b, output sum, output carry);
    assign sum = a ^ b;
    assign carry = a & b;
endmodule

4. What is the difference between a module and an instance in Verilog?

• Module: A module is the basic building block in Verilog that defines a design block with ports and functionality. It is like a blueprint or template.
• Instance: An instance is a specific copy of a module that is used in a design. Multiple instances of the same module can exist in a design. Port mapping by order and Port mapping by name are two different ways of Port Mapping for Module Instantiation in Verilog.

Example:

module full_adder(
    input a,b,cin,
    output sum,carry
);

wire c1,c2,s;

// This example uses the half_adder module from the example of Question number 3
half_adder ha0(a,b,s,c1); // Port mapping by order
half_adder ha1(.a(cin), .b(s), .carry(c2), .sum(sum)); // Port mapping by name

assign carry = c1 | c2 ;

endmodule

5. What is the difference between wire and reg?

6. What is the difference between always and initial blocks?

always block runs repeatedly during simulation; whereas, initial block executes once at the start of simulation.

7. What is the purpose of the always block in Verilog?

The always block is essential for defining behaviors that are continuously sensitive to changes in specified signals. It is widely used to describe both combinational and sequential logic in Verilog. For combinational logic, sensitivity is typically to all inputs, while for sequential logic, it is usually sensitive to clock edges.

Example of always block for combinational logic:

// 2-to-1 multiplexer using an always block sensitive to any input changes
module mux2to1 (
    input wire a,
    input wire b,
    input wire sel,
    output reg y
);

always @(*) begin
    if (sel)
        y = b;
    else
        y = a;
end

endmodule

Explanation:

• The always @(*) sensitivity list means the block runs whenever any input changes (combinational logic).
• The output y updates immediately based on inputs a, b, and sel.
• No clock is involved; output changes as inputs change.

Example of always block for sequential logic:

// positive-edge triggered D flip-flop with synchronous reset
module d_ff (
    input wire clk,
    input wire reset,
    input wire d,
    output reg q
);

always @(posedge clk) begin
    if (reset)
        q <= 0;
    else
        q <= d;
end

endmodule

Explanation:

• The always @(posedge clk) block triggers only on the rising edge of the clock (clk).
• If reset is asserted, the output q is cleared to 0 synchronously.
• Otherwise, q captures the input d on the clock edge.
• This models sequential logic (flip-flop behavior).

8. What is the purpose of the initial block in Verilog?

The initial block in Verilog is used to specify code that runs once at the very beginning of a simulation. It’s typically used for setting up initial conditions, such as initializing registers or variables before the design starts operating. Unlike always blocks, which run repeatedly based on events, the initial block executes only one time. This makes it useful for testbenches or for providing default values in simulation. However, initial blocks are generally not synthesizable for hardware implementation, so they are mostly used for simulation purposes.

9. What is the significance of timescale directive?

timescale directive defines time unit and precision (resolution) for delays in simulation, ensuring accurate timing in simulations (`timescale time_unit/time_precision). E.g., `timescale 1ns/1ps – This means 1 unit of simulation time delay is 1ns (#1 means 1ns). And time_precision decides how time delay would be rounded before being used in the simulation (#3.27651 will be rounded to 3.277ns and #3.27449 will be rounded to 3.274ns).

10. What are the different data types in Verilog?

The common data types in Verilog are:

• wire: Represents a connection.
• reg: Represents a storage element.
• integer: Used for general-purpose integer variables.
• real: Used for real numbers.
• time: Used for simulation time.
• parameter: Used for defining constants.

Basic Verilog Questions Part 2