Module Instantiation in Verilog

A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface.

The process of creating objects from a module template is called instantiation, and the objects are called instances. Each instance is a complete, independent and concurrently active copy of a module. A module can be instantiated in another module thus creating hierarchy.

Syntax:

Module_name  Instance_name (Port_Association_List)

Module instantiation consists of module_name followed by instance_name and port_association_list. Need of instance_name is, we can have multiple instance of same module in the same program. Instance name should be unique for each instance of the same module. Port_association_list shows how ports are mapped.

Let us take an example of 4-bit adder for explaining module instantiation.

Module for 1-bit adder is fulladd as shown below.

module fulladd(s, c_out, ain, bin, c_in);
   output s, c_out;
   input ain, bin, c_in;
   assign s = (ain^bin)^c_in; // sum bit
   assign c_out = (ain & bin) | (bin & c_in) |(c_in & ain); //carry bit
endmodule

The above 1-bit adder is instantiated ‘4’ times to get functionality of 4-bit adder i.e. fulladder_4bit. Each instance of full adder has different instance name and port association list.

module fulladder_4bit(sum, cout, a, b, cin);
//input output port declarations
   output [3:0] sum;
   output cout;
   input [3:0] a, b;
   input cin;
   wire c1, c2, c3;
// Instantiate four 1-bit full adders
   fulladd f0 (sum[0], c1, a[0], b[0], cin);
   fulladd f1 (sum[1], c2, a[1], b[1], c1);
   fulladd f2 (sum[2], c3, a[2], b[2], c2);
   fulladd f3 (sum[3], cout, a[3], b[3], c3);
endmodule

In the above example, 4-bit adder module is the top level module thus creating an hierarchy.

While calling a module the width of each port must be the same, eg, a 4-bit register can not be matched to a 2-bit register. This is known as port matching. Port mapping can be done in two different ways i.e. “Port mapping by order” and “Port mapping by name“.

Reference: Verilog HDL, A guide to Digital Design and Synthesis; Samir Palnitkar