Difference between Combinational and Sequential logic circuits.

Combinational and Sequential circuits are the most essential concepts to be understood in digital electronics.

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Sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs.

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Combinational Logic CircuitsSequential Logic Circuits
Output is a function of the present inputs (Time Independent Logic).Output is a function of clock, present inputs and the previous states of the system.
Do not have the ability to store data (state).Have memory to store the present states that is sent as control input (enable) for the next operation.
It does not require any feedback. It simply outputs the input according to the logic designed.It involves feedback from output to input that is stored in the memory for the next operation.
Used mainly for Arithmetic and Boolean operations.Used for storing data (and hence used in RAM).
Logic gates are the elementary building blocks.Flip flops (binary storage device) are the elementary building unit.
Independent of clock and hence does not require triggering to operate.Clocked (Triggered for operation with electronic pulses).
Example: Adder [1+0=1; Dependency only on present inputs i.e., 1 and 0].Example: Counter [Previous O/P +1=Current O/P; Dependency on present input as well as previous state].

24 comments for “Difference between Combinational and Sequential logic circuits.

    • Hey Gautam,
      To design sequential circuit also we use gates. But in case of sequential circuit we use feed back gates (memory elements) along with combinational logic. So that it can work like a latch or flip-flop. If you still have doubt, let us know. We would explain it in a detailed way.

  1. In sequential circuit block diagram ,it is said that some outputs are again feedbacked to inputs,after storing them in memory.
    But,where is that memory in sr latch.In sr latch ,it is seen that the output is directly taken to the inputs,and their is no memory.

    • Dear Sagnik,

      Memory in the block diagram shows a delay for which the previous output can be hold and can be used as the feedback input in the present clock cycle. In the SR latch the gate delay in the NAND/NOR gates works like the memory block in the block diagram. So, there is no explicit memory block in the SR latch.

  2. CAN you please explain with the help of an example that the flip-flop work as a memory element. I have confusion in it.

    • Hi Amit,

      You take an example of shift-register or a counter. Basic elements of both of these are flip-flops.
      Let’s consider a 3-bit counter. It counts 000,001,010,011,100,101,110 and 111.
      Let a is the counter. Then it can be written as:
      a(t+1) = a(t) + 1
      so, ‘a’ at time t+1 can be calculated only when ‘a’ holds a value at time ‘t’. Thus it behaves like a memory.

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