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Category: VLSI Technology

Checking ERC (Well Check)

Posted on November 6, 2018June 17, 2025 By vlsifacts No Comments on Checking ERC (Well Check)

This process checks the connection of the n-well and p-substrate. The C5 process used here is an n-well process. The p-type substrate is common to all NMOS devices and should be grounded. One of the electrical rule checks (ERCs) is to verify that the p-well (in this case p-substrate) is always connected to ground. Further,…

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Electric

Layout vs. Schematic (LVS)

Posted on November 6, 2018June 17, 2025 By vlsifacts 1 Comment on Layout vs. Schematic (LVS)

Layout vs. Schematic (LVS) in Electric is checked using Network Consistency Checking (NCC) To check this, execute Tools –> NCC –> Schematic and Layout views of Cell in Current Window. You can run this command being in any design window (schematic / layout). We can execute the above command by only pressing ‘L‘ as we have…

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Electric

Key Binding in Electric

Posted on November 6, 2018June 17, 2025 By vlsifacts No Comments on Key Binding in Electric

Key Binding binds a key; when pressed will execute a command from the menu to which it is bound. You can bind a key to a command as below: Go to File -> Preferences –> Categories –> General –> Key bindings Then in Key Binding USER Preferences we can choose any command to assign a…

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Electric

Checking of DRC (Design Rule Check)

Posted on November 6, 2018June 17, 2025 By vlsifacts No Comments on Checking of DRC (Design Rule Check)

We should keep on checking the Design Rule Check throughout designing (both in case of schematic and layout) to make sure whether there is any error or not. To check DRC you can execute Tools –> DRC –> Check Hierarchically or you can press F5. Once DRC is checked, you can see result in the…

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Electric

Creating Resistor Layout

Posted on November 6, 2018June 17, 2025 By Sidhartha No Comments on Creating Resistor Layout

Create a new cell as in case of schematic earlier with the view as {layout} and with the same cell name Resistive_divider. Now under the library design_1.jelib you can find a layout cell named as Resistive_divider {lay} with an yellow indicator as follows: Create an N-Well Resistor layout by clicking the menu item (bottom left-hand side of…

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Electric

Creating Resistor Schematic

Posted on November 6, 2018June 17, 2025 By Sidhartha 2 Comments on Creating Resistor Schematic

1. Let’s create a Library Go to Explorer (beside the Components view); you will find LIBRARIES name as noname File –> Save Library As Go to the location where you want to save your design (eg: $PATH/Electric/Designs) Name the design (library name) eg. design_1.jelib We would create our schematic and layout under this library Now you…

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Electric

Starting and Setting-up Electric

Posted on November 5, 2018June 17, 2025 By Sidhartha No Comments on Starting and Setting-up Electric

1. Start Electric: You will see the following window. 2. Towards the bottom of the window, you will find an Electric Messages Window where you can find different messages throughout any design. 3. You can change the background color of the window as follows Window –> Color Schemes –> White Background Colors 4.  First of all we…

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Electric

Getting Started with Electric

Posted on November 5, 2018June 17, 2025 By Sidhartha No Comments on Getting Started with Electric

Installation Steps: Download and save electric-9.07.jar Click here to download electric-9.07 Download the Electric Source Release (26 MB) Create the folder $PATH/Electric and save the file electric-9.07.jar in it Note: It is up to you where you want to keep the electric jar file. But I would advise to create a folder name Electric and open the electric…

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Electric

ESD Models and their comparison – ESD Part 2

Posted on January 26, 2018June 17, 2025 By Jitendra No Comments on ESD Models and their comparison – ESD Part 2

In the part-1 of ESD we learnt through of ESD testing and its importance. ICs are susceptible to ESD event as they consist of components that are very sensitive to excess current and voltage. ESD even can occur at any point in time during IC assembly and packaging, part handling or system assembly. Important point…

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VLSI Circuits, VLSI Technology

Electro-Static Discharge (ESD) – VLSI Circuit’s Prospective

Posted on January 15, 2018June 17, 2025 By Jitendra No Comments on Electro-Static Discharge (ESD) – VLSI Circuit’s Prospective

Electro Static Discharge (ESD) is sudden flow of static electricity between two electrically charged objects for a very short duration of time. The study of ESD phenomenon and its protection circuits are more relevant with each technology nodes as smaller devices are more vulnerable. Electric Over-Stress (EOS) is also one by-product of ESD which also…

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VLSI Circuits

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