Electro Static Discharge (ESD) is sudden flow of static electricity between two electrically charged objects for a very short duration of time. The study of ESD phenomenon and its protection circuits are more relevant with each technology nodes as smaller devices are more vulnerable. Electric Over-Stress (EOS) is also one by-product of ESD which also needs to be taken care of. EOS happens when any component is operated beyond its absolute maximum ratings. Just to give a glimpse of criticality of ESD, here is a chart showing failure rates associated with various reliability issues.
Looking at ESD from failure point of view, both ESD and EOS contributes to more than 50% of reliability problems. These reliability problems will degrade circuits FIT (Failure in time) rate, one of the key spec for any IC. Although ESD stress is for shorter duration, it can cause permanent functional issues such as Electro-Migration (EM), Oxide Stress, and Electrical Overstress etc. ESD and EOS both also affects the production yield and therefore are of utmost importance from a circuit designer point of view.
Now let’s see how ESD influences Integrated circuits (ICs) and why we, as an IC design engineer, should be worried about ESD???
In most simplistic way, ESD voltage on any device creates a large surge current which will flow through ohmic drops and if these resistances are large enough then it will create huge internal voltages. These large internal voltage are in turn responsible for EOS which can cause damage to the device. Generally there are dedicated specialist team to design ESD protection circuit but as an IC design engineer we need to know how these ESD protection circuits are influencing our circuit’s performance. Also the design of our circuit also influences the choice of the ESD protection circuit to be used. Hence we must be well aware of the ESD as a phenomenon and ways to protect our circuits from ESD.
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[1] Prof. Phillip E. Allen, Online Lecture Series on ESD: An Analog Design Viewpoint