Category: Verilog

Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

March 29, 2016June 17, 2025 Dewansh No Comments

There are Two types of Procedural Assignments in Verilog. To learn more about Delay: Read Delay in Assignment (#) in Verilog Blocking assignments Example: Non-Blocking assignments Example: To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments The following example shows interactions between blocking and non-blocking for simulation only (not…

Verilog

Delay in Assignment (#) in Verilog

March 29, 2016June 17, 2025 vlsifacts No Comments

Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment delay: variable = #Δt expression; // “expression” gets evaluated at time 0 but gets assigned to the “variable”…

Verilog

Synthesis and Functioning of Blocking and Non-Blocking Assignments.

March 20, 2016June 17, 2025 Priyadarshi No Comments

Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. The following example illustrates the Blocking Assignment Wave forms for the above exampleThe following example illustrates the Non-Blocking Assignment Wave forms for the above example…

DHD, Digital Electronics, Uncategorized, Verilog, VLSI Circuits, Xilinx

Port Mapping for Module Instantiation in Verilog

February 25, 2016June 17, 2025 vlsifacts No Comments

Port mapping in module instantiation can be done in two different ways: In this post, we would take one example to understand both types of port mapping in detail. The above Figure shows an example for module instantiation. Figure shows module “SYNCHRO” which consists of 2 ‘D’ flip-flops and are connected in serial fashion. Module “SYNCHRO”…

Verilog

Module Instantiation in Verilog

February 25, 2016June 17, 2025 vlsifacts No Comments

A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. Each…

Verilog

Ports in Verilog Module

February 23, 2016June 17, 2025 vlsifacts No Comments

Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All ports declared as one of the above is assumed to be a wire by default,…

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Verilog

Module Definition in Verilog

February 21, 2016June 17, 2025 vlsifacts 2 Comments

A “module” is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. Module interface refers, how module communicates with external world. This communication…

Verilog

Different Coding Styles of Verilog Language

January 31, 2016June 16, 2025 vlsifacts 4 Comments

Verilog language has the capability of designing a module in several coding styles. Depending on the needs of a design, internals of each module can be defined at four level of abstractions. Irrespective of the internal abstraction level, the module would behave exactly in the similar way to the external environment. Following are the four…

DHD, Verilog, Xilinx

Synopsys – Interview Questions – based on Synthesis and Simulation

January 19, 2016June 16, 2025 Priyadarshi No Comments

This post contains some very interesting interview questions asked by Synopsys the EDA giant in its interview. The questions are based on Verilog Synthesis and Simulation. Though I have included the answers; I would encourage the reader to experiment himself or herself and then discuss these in the forum. 1. How a latch gets inferred…

DHD, Digital Electronics, Interview, Interview Experience, Verilog

Case and Conditional Statements Synthesis CAUTION !!!

November 12, 2015June 16, 2025 Priyadarshi 5 Comments

Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by programming its functionality. Let’s say, we have to design a circuit that selects a particular…

DHD, Digital Electronics, Verilog