Category: Verilog

Basic Verilog Questions for Beginners (Part – 3) : Build Your Foundations

June 25, 2025July 18, 2025 vlsifacts No Comments

1. Explain the concept of sensitivity lists in Verilog. A sensitivity list specifies the signals that trigger the execution of an always block when they change. Example: Here, the block executes whenever a or b changes. 2. What is the purpose of generate statements in Verilog? The generate statement is used to dynamically create repetitive hardware structures or conditional instantiations during elaboration. Example: 3. Discuss…

Interview, Question Bank, Verilog

Basic Verilog Questions for Beginners (Part – 2) : Build Your Foundations

June 24, 2025July 18, 2025 vlsifacts No Comments

1. Explain the difference between blocking and non-blocking assignments. Example: 2. What is the difference between posedge and negedge? Example: 3. What is the purpose of the assign statement? The assign statement is used for continuous assignments in combinational logic. It is used to drive values to wire data types. Example: 4. How do you declare a parameter in Verilog? A parameter is…

Interview, Question Bank, Verilog

Basic Verilog Questions for Beginners (Part – 1) : Build Your Foundations

June 24, 2025July 18, 2025 vlsifacts No Comments

1. What is Verilog and why is it used in VLSI design? Verilog is a Hardware Description Language (HDL) widely used to design and model digital electronic systems. It helps in writing structured, reusable code to describe how a circuit should function. Verilog is crucial in VLSI design because it supports simulation, verification, and hardware…

Interview, Question Bank, Verilog

Is an “initial” Block Synthesizable in Verilog?

June 20, 2025June 20, 2025 vlsifacts No Comments

When working with Verilog for digital design, one common question that arises is whether the initial block is synthesizable. The short answer is generally no. initial blocks are primarily meant for simulation and testbench purposes, not for actual hardware synthesis. What is an initial Block? The initial block in Verilog is used to set initial values for signals or variables at the very…

Verilog

Difference between $display, $monitor, $write and $strobe in Verilog

March 15, 2023June 19, 2025 vlsifacts No Comments

Although all $display, $monitor, $write and $strobe in System Verilog seem to be similar, there is a slight difference. $display is the normal display, which executes its parameters wherever it is present in the code. $write is similar to $display except that $display displays the contents in the next line (cursor moves to the next…

Verilog

Synthesis in VLSI

November 18, 2019June 17, 2025 Dewansh No Comments

Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by the designer. In simple language, Synthesis is a process that converts the abstract form of design to a properly implemented chip in terms of logic gates. Synthesis takes place in multiple steps: There are various tools which can…

Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

March 29, 2016June 17, 2025 Dewansh No Comments

There are Two types of Procedural Assignments in Verilog. To learn more about Delay: Read Delay in Assignment (#) in Verilog Blocking assignments Example: Non-Blocking assignments Example: To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments The following example shows interactions between blocking and non-blocking for simulation only (not…

Verilog

Delay in Assignment (#) in Verilog

March 29, 2016June 17, 2025 vlsifacts No Comments

Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment delay: variable = #Δt expression; // “expression” gets evaluated at time 0 but gets assigned to the “variable”…

Verilog

Synthesis and Functioning of Blocking and Non-Blocking Assignments.

March 20, 2016June 17, 2025 Priyadarshi No Comments

Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. The following example illustrates the Blocking Assignment Wave forms for the above exampleThe following example illustrates the Non-Blocking Assignment Wave forms for the above example…

DHD, Digital Electronics, Uncategorized, Verilog, VLSI Circuits, Xilinx

Port Mapping for Module Instantiation in Verilog

February 25, 2016June 17, 2025 vlsifacts No Comments

Port mapping in module instantiation can be done in two different ways: In this post, we would take one example to understand both types of port mapping in detail. The above Figure shows an example for module instantiation. Figure shows module “SYNCHRO” which consists of 2 ‘D’ flip-flops and are connected in serial fashion. Module “SYNCHRO”…

Verilog