Let's Program the Transistors
This post illustrates the circuit design of Sequence Detector for the pattern “1101”. State Machine diagram for the same Sequence Detector has been shown below. Click here to realize how we reach to the following state transition diagram. Click here to learn the step by step procedure of “How to synthesize a state machine / How…
Sequence Detector is a digital system which can detect/recognize a specified pattern from a stream of input bits. Let’s say the Sequence Detector is designed to recognize a pattern “1101”. Consider input “X” is a stream of binary bits. When the Sequence Detectors finds consecutive 4 bits of input bit stream as “1101”, then the…
Read More “State Machine Diagram for Pattern Recognition / Sequence Detector” »
State machine synthesis is a process of of boiling down a state machine to a digital logic circuit. Steps in State Machine Synthesis Let’s achieve the state machine realization of the following state diagram Let’s assume that we have completed the first two steps mentioned above and achieved a minimized Mealy state machine as shown…
Flipflops to be considered are: SR Flipflop S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Invalid inputs Characteristic Equation Q(t+1) = R'(t)Q(t) + S(t) ; S(t)R(t) = 0 Excitation Table Q(t) Q(t+1) S R 0 0 0 x 0 1 1 0 1 0 0 1 1 1 x…
Read More “Truth Tables, Characteristic Equations and Excitation Tables of Different Flipflops” »
Sequential machines can be designed in two different ways: (i) Mealy Machine & (ii) Moore Machine Considering Mealy or Moore for the designing of sequential machine, it’s actually difficult to draw a hard line where one machine is always better than the other. Depending on the application requirement one may dominate the other. It is…
Read More “Mealy to Moore and Moore to Mealy Transformation” »
Design of sequential circuit can be composed of designing combinational circuit and state register. Sequential circuits are implemented in two different ways: We can represent a sequential machine as M = <I,O,S,f,g>; where I: Input setO: Output setS: State spacef: A function mapping IxS = Og: A function mapping IxS = S Let’s understand both…
This post contains some very interesting interview questions asked by Synopsys the EDA giant in its interview. The questions are based on Verilog Synthesis and Simulation. Though I have included the answers; I would encourage the reader to experiment himself or herself and then discuss these in the forum. 1. How a latch gets inferred…
Read More “Synopsys – Interview Questions – based on Synthesis and Simulation” »
Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by programming its functionality. Let’s say, we have to design a circuit that selects a particular…
Read More “Case and Conditional Statements Synthesis CAUTION !!!” »
Problem Statement: Design a circuit for an edge triggered 4-bit binary up counter (0000 to 1111). When it reaches “1111”, it should revert back to “0000” after the next edge. Use positive edge triggered D flip-flop (shown in the below figure) to design the circuit. Pin Input / Output Description D Input Data Input CLK…
Read More “Circuit Design of a 4-bit Binary Counter Using D Flip-flops” »
Flip-Flop (FF) and Latch are digital electronic circuits that are used to store information in bits as they have two stable states. One FF or latch can store 1 bit of information. FF is a circuit that can be made to change its state by applying signals to one or more control inputs and will have…