Basic Verilog Questions for Beginners (Part – 3) : Build Your Foundations

1. Explain the concept of sensitivity lists in Verilog.

A sensitivity list specifies the signals that trigger the execution of an always block when they change.

Example:

always @(a or b) begin //here a and b are sensitivity lists
    y = a & b;
end

Here, the block executes whenever a or b changes.

2. What is the purpose of generate statements in Verilog?

The generate statement is used to dynamically create repetitive hardware structures or conditional instantiations during elaboration.

Example:

genvar i;
generate
    for (i = 0; i < 4; i = i + 1) begin : gen_block
        assign out[i] = a[i] & b[i];
    end
endgenerate

3. Discuss the difference between == and === operators.

The == operator in Verilog performs logical equality comparison, treating unknown (X) and high-impedance (Z) bits as don’t-cares, so it may consider two values equal even if some bits are unknown or high-impedance. In contrast, the === operator performs a case equality comparison, checking both the value and the exact bit states, including X and Z, meaning two values are equal only if all bits match exactly, including unknowns.

Example:

reg [1:0] a = 2'b1X;
reg [1:0] b = 2'b10;

initial begin
    $display("a == b : %b", (a == b));   // Output: 1 (true)
    $display("a === b: %b", (a === b));  // Output: 0 (false)
end

Here, a == b returns true because X is treated as don’t-care, but a === b returns false because the unknown bit in a does not exactly match the known bit in b.

For synthesis, equality checks typically use == without considering unknown states, focusing only on binary logic values. However, the == and === operators are not synthesizable, when they are primarily used for comparison during simulation and verification, especially to handle unknown (X) and high-impedance (Z) states which do not exist in actual hardware. Their main use is in testbenches and assertion checks to verify design correctness and debug simulation behavior. 

4. What is the use of include directive in Verilog?

The include directive in Verilog is used to import external Verilog source files into your current design file. It allows you to reuse common definitions, macros, parameters, or modules across multiple files without duplicating code.

Syntax:

`include "filename.v"

Key Points:

• The included file’s content is textually inserted at the location of the include directive during compilation.
• Often used to include definition files (defs.v) containing macros (\define`), parameters, or commonly used code snippets.
• Helps maintain modular and organized code, promoting reusability and easier maintenance.
• The filename is usually enclosed in double quotes " " and is relative to the compilation directory.

Example:

`include "defs.v"

module my_module;
    // Use macros or parameters defined in defs.v
endmodule

5. What is the difference between task and function in Verilog?

Task: A task in Verilog is a block of code that can perform complex operations, including those that involve delays (#), event control, and multiple input/output arguments. Tasks do not return a value directly but can modify multiple output or inout arguments, making them suitable for modeling behaviors that require time or multiple results.

Function: A function is a simpler construct designed to compute and return a single value without any delay or event control statements. Functions must execute in zero simulation time and cannot contain timing controls, making them ideal for combinational calculations or expressions that need to be evaluated immediately.

6. Discuss the difference between behavioral and structural Verilog model.

Behavioral Verilog models describe the functionality of a design using high-level constructs such as always blocks, if statements, and loops, focusing on what the design does rather than how it is built. This style allows designers to write concise and abstract code that specifies the behavior of circuits without detailing the exact hardware structure.

In contrast, structural Verilog models explicitly describe the design by instantiating and connecting lower-level modules or primitives, representing the hardware as a network of interconnected components. Structural modeling is closer to the physical implementation and is useful for hierarchical design and detailed hardware representation.

Refer to Different Coding Styles of Verilog Language to find a more detailed discussion with examples for question number 6.

7. How to implement combinational logic in Verilog?

To implement combinational logic in Verilog, you can use either continuous assignments with the assign statement or procedural assignments inside an always @(*) block. The assign statement continuously drives a wire with the result of a combinational expression, such as assign y = a & b;, which is simple and efficient for straightforward logic.

Alternatively, an always @(*) block allows you to describe more complex combinational behavior using blocking assignments (=) and control statements like if or case, ensuring the output updates whenever any input changes.

Both methods ensure that the output reflects the current inputs immediately, modeling combinational circuits without memory or delays.

8. What is the significance of default case?

The default case in a case statement provides a defined behavior for any input values not explicitly listed in the case items. Including a default prevents unintended memory elements, such as latches, from being inferred during synthesis by ensuring the output is assigned for all possible inputs. This makes the design more robust and predictable, avoiding simulation-synthesis mismatches and potential functional bugs.

Example without default (Possible latch inference)

module latch_example(
    input  wire [1:0] sel,
    input  wire       in0,
    input  wire       in1,
    output reg        out
);

always @(*) begin
    case (sel)
        2'b00: out = in0;
        2'b01: out = in1;
        // No default case here
    endcase
end

endmodule

What happens:

• When sel is 2'b10 or 2'b11, out is not assigned any value inside the case.
• To retain its previous value, synthesis infers a latch to hold out.
• Latches can cause unintended behavior and timing issues.

Example with default (No latch inferred)

module no_latch_example(
    input  wire [1:0] sel,
    input  wire       in0,
    input  wire       in1,
    output reg        out
);

always @(*) begin
    case (sel)
        2'b00: out = in0;
        2'b01: out = in1;
        default: out = 1'b0;  // Default assignment ensures out is always driven
    endcase
end

endmodule

What happens:

• For any sel value not explicitly listed, out is assigned 0.
• This prevents latch inference because out is always assigned a value.
• The design becomes more predictable and synthesizable as purely combinational logic.

Summary:

• Without default: Missing assignments cause latches to be inferred.
• With default: All cases are covered, preventing unintended latches.

9. Discuss the use of $display and $monitor in Verilog simulation.

$display outputs the specified message or variable values only once at the point where it is called during simulation, making it useful for printing snapshots or specific events.

In contrast, $monitor continuously watches the listed variables and automatically prints their values whenever any of them change, providing ongoing tracking of signal activity throughout the simulation.

Refer to Difference between $display, $monitor, $write and $strobe in Verilog to find a more detailed discussion with examples for question number 9.

10. What is the difference between wire and tri?

A wire in Verilog is a basic net used to connect different parts of a design and represents simple, single-driven signals.

In contrast, a tri net explicitly models tri-state behavior, allowing multiple drivers to drive the net with the possibility of high-impedance (Z) states, which is useful for modeling buses or shared lines where signals can be driven or released by different sources.

Basic Verilog Questions Part2