Basic Verilog Questions for Beginners (Part – 2) : Build Your Foundations

1. Explain the difference between blocking and non-blocking assignments.

• Blocking (=): Executes sequentially, typically for combinational logic. The next statement is executed only after the current statement is completed.
• Non-blocking (<=): Schedules updates concurrently (executes in parallel), typically for sequential logic. All non-blocking assignments in the same time step are evaluated simultaneously.

Example:

// Do not mix-up both blocking and non-blocking assignments in a single procedural block. Here, it has done for understanding purpose.
always @(posedge clk) begin
    a = b; // Blocking
    c <= d; // Non-blocking
end

2. What is the difference between posedge and negedge?

• posedge: Refers to the rising edge of a signal (low-to-high transition).
• negedge: Refers to the falling edge of a signal (high-to-low transition).

Example:

always @(posedge clk) begin
    // Code executes on the rising edge of clk
end

3. What is the purpose of the assign statement?

The assign statement is used for continuous assignments in combinational logic. It is used to drive values to wire data types.

Example:

assign y = a & b; // y is continuously assigned the value of a AND b.

4. How do you declare a parameter in Verilog?

A parameter is declared using the parameter keyword. It is used to define constants.

Example:

module my_module #(parameter WIDTH = 8) (input [WIDTH-1:0] a, b, output [WIDTH-1:0] c);
    assign c = a + b;
endmodule

// Above example can also be written as below:

module my_module (a, b, c);

    parameter WIDTH = 8;
    input [WIDTH-1:0] a, b;
    output [WIDTH-1:0] c;

    assign c = a + b;
endmodule

5. What is the difference between parameter and localparam?

• parameter: Can be overridden during module instantiation.
• localparam: Cannot be overridden and is used for internal constants.

Example with parameter (Overridable)

module example_parameter #(parameter WIDTH = 8) (
    input wire [WIDTH-1:0] in,
    output wire [WIDTH-1:0] out
);
    assign out = in;
endmodule

Explanation:

• WIDTH is a parameter with a default value of 8.
• When you instantiate this module, you can override WIDTH to change the bit-width.

example_parameter #(.WIDTH(16)) inst1 (.in(data_in), .out(data_out));

Here, WIDTH is overridden to 16 for inst1.

Example with localparam (Non-overridable)

module example_localparam (
    input wire [3:0] in,
    output wire [3:0] out
);
    localparam WIDTH = 4;
    wire [WIDTH-1:0] temp;
    assign temp = in;
    assign out = temp;
endmodule

Explanation:

• WIDTH is a localparam, set internally and cannot be overridden during instantiation.
• It is used for internal constants or calculations within the module.

Summary:

• parameter: Can be changed from outside the module during instantiation to customize behavior.
• localparam: Fixed inside the module, used for constants that should not be changed externally.

6. What is the significance of # in Verilog?

The # symbol is used to specify delays in Verilog. For example:

assign #5 y = a & b; // Output y is delayed by 5 time units.

7. Explain about Signed and unsigned data types?

• Unsigned data types represent only non-negative numbers (0 and positive integers). By default, Verilog treats reg and wire as unsigned unless specified otherwise. Arithmetic operations on unsigned types assume values are always positive.
• Signed data types can represent both positive and negative numbers using two’s complement representation. To declare a signed variable, you explicitly use the signed keyword.

Example:

module signed_unsigned_example;
    reg [7:0] unsigned_val;        // Unsigned 8-bit
    reg signed [7:0] signed_val;  // Signed 8-bit

    initial begin
        unsigned_val = 8'b11111111;  // 255 decimal
        signed_val = 8'b11111111;    // -1 decimal (two's complement)

        $display ("Unsigned value = %d", unsigned_val); // Prints: 255
        $display ("Signed value = %d", signed_val);    // Prints: -1
    end
endmodule

Summary:

• Use unsigned for values that never go negative (e.g., addresses, counters).
• Use signed when negative values and arithmetic with sign matter (e.g., signed calculations, offsets).

8. Declare a 2D array in Verilog?

reg [7:0] array [0:15]; // 8-bit wide, 16 elements

Explanation:

• The first dimension ([7:0]) defines the width of each element (8 bits).
• The second dimension ([0:15]) defines the number of elements (16).

So, you can think of it as a 2D structure: 16 rows × 8 columns (bits).

9. Explain procedural vs. continuous assignment?

Procedural assignments in Verilog occur inside always or initial blocks and allow you to describe complex behavior that can depend on events such as clock edges or changes in signals. These assignments use variables declared as reg and can implement both combinational and sequential logic by controlling when and how values update. In contrast, continuous assignments use the assign keyword outside procedural blocks to drive wire types continuously, reflecting changes in real time without waiting for events. Continuous assignments are typically used for simple combinational logic where the output is directly and continuously driven by input expressions. Together, these two methods provide flexibility to model both hardware behavior that changes over time and simple real-time signal relationships.

10. What is a testbench?

A testbench is a special Verilog module used to simulate and verify the functionality of a design under test (DUT) by applying input stimuli and observing the outputs. It does not represent hardware itself but serves as a controlled environment to validate that the design behaves as expected before synthesis or implementation. Testbenches typically generate test vectors, apply them to the DUT, and may include checks or monitors to automate verification.

Example:

module simple_testbench;
    reg a, b;
    wire y;

    // Instantiate the design under test (DUT)
    and_gate dut (.in1(a), .in2(b), .out(y));

    initial begin
        // Apply test vectors
        a = 0; b = 0; #10;
        a = 0; b = 1; #10;
        a = 1; b = 0; #10;
        a = 1; b = 1; #10;
        $finish;
    end
endmodule

module and_gate(input in1, input in2, output out);
    assign out = in1 & in2;
endmodule

This testbench applies different input combinations to a simple AND gate and allows you to observe the output during simulation.

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