Parity generator can be of two types: (i) Even Parity Generator (ii) Odd Parity Generator In this post we will derive the state machine for an even parity generator. Consider input “I” is a stream of binary bits. When an…
Author: vlsifacts
Circuit Design of a Sequence Detector
This post illustrates the circuit design of Sequence Detector for the pattern “1101”. State Machine diagram for the same Sequence Detector has been shown below. Click here to realize how we reach to the following state transition diagram. Click here to…
State Machine Diagram for Pattern Recognition / Sequence Detector
Sequence Detector is a digital system which can detect/recognize a specified pattern from a stream of input bits. Let’s say the Sequence Detector is designed to recognize a pattern “1101”. Consider input “X” is a stream of binary bits. When…
State Machine Synthesis
State machine synthesis is a process of of boiling down a state machine to a digital logic circuit. Steps in State Machine Synthesis Let’s achieve the state machine realization of the following state diagram Let’s assume that we have completed…
Truth Tables, Characteristic Equations and Excitation Tables of Different Flipflops
Flipflops to be considered are: SR Flipflop S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Invalid inputs Characteristic Equation Q(t+1) = R'(t)Q(t) + S(t) ; S(t)R(t) = 0 Excitation Table Q(t) Q(t+1) S R…
Mealy to Moore and Moore to Mealy Transformation
Sequential machines can be designed in two different ways: (i) Mealy Machine & (ii) Moore Machine Considering Mealy or Moore for the designing of sequential machine, it’s actually difficult to draw a hard line where one machine is always better…
Mealy Vs. Moore Machine
Design of sequential circuit can be composed of designing combinational circuit and state register. Sequential circuits are implemented in two different ways: We can represent a sequential machine as M = <I,O,S,f,g>; where I: Input set O: Output set S:…
Different Coding Styles of Verilog Language
Verilog language has the capability of designing a module in several coding styles. Depending on the needs of a design, internals of each module can be defined at four level of abstractions. Irrespective of the internal abstraction level, the module…
Interview Experience – WIPRO GMT (Global Media & Telecom ) – (On Campus – #2)
I am Jitendra Kumar Yadav, Jaypee Institute of Information Technology. This is my interview experience for the post of Project Engineer at Wipro Limited. I have described my selection process for the mentioned post in the following content. Check here the first post…
Digilent Design Contest 12th Edition
Do you love to play with FPGAs? If yes, then there is a golden opportunity to showcase your talent. Digilent Design Contest Europe Region has reached its 12th Edition, with a rich history behind, many interesting and cool projects along the…