Let's Program the Transistors
The Synopsys University Program announces the 2016 student design contest in India featuring Synopsys Custom Design tools. This contest gives students the opportunity to showcase their talent in electronic design. Teams selected to compete in the contest will receive a free 3-day training workshop hosted by Synopsys and the chance to win a cash prize….
Mentor Graphics Corporation founded the Higher Education Program in 1985 to further the development of skilled engineers within the electronics industry. The program provides colleges and universities with leading edge design tools for classroom instruction and academic research to help ensure that engineering graduates enter into industry proficient with state-of-the-art tools and techniques. “Verification of…
Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment delay: variable = #Δt expression; // “expression” gets evaluated at time 0 but gets assigned to the “variable”…
There are two basic types of digital design methodologies: top-down Design Methodology In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided. bottom-up Design Methodology…
“There is Plenty of Room at the Bottom“ A popular talk delivered by Richard Feynman to American Physical Society at California Institute of Technology in the year of 1959. This talk at that time could foresee the possibility of the revolution which has been brought by VLSI today. The term VLSI stands for Very Large…
Port mapping in module instantiation can be done in two different ways: In this post, we would take one example to understand both types of port mapping in detail. The above Figure shows an example for module instantiation. Figure shows module “SYNCHRO” which consists of 2 ‘D’ flip-flops and are connected in serial fashion. Module “SYNCHRO”…
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A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. Each…
Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All ports declared as one of the above is assumed to be a wire by default,…
A “module” is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. Module interface refers, how module communicates with external world. This communication…
The states which are equivalent, are redundant. Because by looking at the output, we can not even figure out in which state the machine is in. So, if there are two equivalent states then there is no point of using both the states. We can merge both the states and can use only one state….