Verilog vs VHDL

Verilog and VHDL are Hardware Description languages (HDL) that are used to describe the behavior and structure of electronic systems. HDL languages are different form software language like ‘C’, as they use concurrency constructs to simulate circuit behavior. HDL includes a means of describing propagation time and signal strength.

Verilog Vs. VHDL

1. Verilog is a weakly typed language as compared to VHDL which is a strongly typed language. This means that Verilog won’t easily compile a script which is not very strongly typed. Intermixing of classes and variables would be difficult in VHDL.
2. Verilog is case sensitive while VHDL is case insensitive.
3. Verilog (more like C) is easier to learn as compared to VHDL. VHDL is much more complicated than Verilog.
4. Verilog unlike VHDL lacks the library management system.