Let's Program the Transistors
The chip design includes different types of processing steps to finish the entire flow. For each and every step, the design process requires a dedicated EDA tool. These tools have the flexibility to import or export different types of files. The picture below shows the various steps of the design flow: Here is a brief…
Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. The following example illustrates the Blocking Assignment Wave forms for the above exampleThe following example illustrates the Non-Blocking Assignment Wave forms for the above example…
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This post contains some very interesting interview questions asked by Synopsys the EDA giant in its interview. The questions are based on Verilog Synthesis and Simulation. Though I have included the answers; I would encourage the reader to experiment himself or herself and then discuss these in the forum. 1. How a latch gets inferred…
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Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by programming its functionality. Let’s say, we have to design a circuit that selects a particular…
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