These are some simple steps which can be used to do the power analysis of a design using Xpower Analyzer which comes readily available in the ISE free web pack.
## Make sure your circuit can be synthesized. Then under the implement design option in the project navigator, Place and Route the design.
## The most common and silly error comes after the Place and Route is “the right chip is not targeted”. This is because most of the free web pack does not support the Artix family, so in the “design properties” under “family“, target another chip: Spartan 3 or Spartan 6 would be fine.
Step – 1
Simulate your design by using a test bench or manually. Power analysis uses the VCD (Value Change Dump) file generated by the simulator for the analysis of the switching power and then do the Placement and routing.
For VCD file generation, use the following code in your test bench.
1 2 3 4 5 6 | initial begin// Change filename as appropriate$dumpfile ("tran_ceiver.vcd");// Dump all the variables in VCD$dumpvars (1,tran_ceiver_test.uut);end |
Step – 2
Under Place and Route, click on the option Analyze Power Distribution.
Step – 3
In the Xpower analyzer go to the file menu and click on the open design. A new window will appear. In that window open your design. The design file would be like “design_name”.ncd. In the Physical Constraint file, select the file “design_name”.pcf (both these files .ncd and .pcf are generated during place and route). finally in the simulation activity add the VCD file “file_name”.vcd
Step – 4
Click “OK” and your power report will be generated.
i am getting duty cycle error how to resolve it
This must be coming while you are dumping the .vcd file, this may happen when the tool does not find relevant information, if you are using all the signals of the design then try using the directive ‘$dumpvars;’ as its is without any file name and hierarchy and use the default file generated by the tool it should be of the name ‘dump.vcd’ or ‘verilog.dump’. I hope your problem gets resolved.
by using saif file i am getting poer report but i am not getting clock option there
I suggest you use a .vcd file as most of the new power tools recommend using a .vcd file.
I am not getting the dynamic power for my design.I generated the vcd file as the it is in the given formats, but the dynamic power is showing 0w.
I am not getting the Dynamic power.It is showing 0watt.
Please check if the clock is showing proper toggling rate. Please check weather you have dumped all the signals correctly. You can use $dumpvars only with no options.