VLSIFacts

Verilog vs VHDL

July 20, 2015June 23, 2025 Dewansh No Comments

Verilog and VHDL are Hardware Description languages (HDL) that are used to describe the behavior and structure of electronic systems. HDL languages are different form software language like ‘C’, as they use concurrency constructs to simulate circuit behavior. HDL includes a means of describing propagation time and signal strength. Verilog Vs. VHDL

DHD, Verilog, VHDL

Advantages and Disadvantages of a Dynamic CMOS Circuit over a Static CMOS Circuit

June 3, 2015May 18, 2025 Dewansh No Comments

Static CMOS circuits use complementary nMOS pulldown and pMOS pullup networks to implement logic gates or logic functions in integrated circuits. Dynamic gates use a clocked pMOS pullup. The implemented logic function or the logic gate is achieved through 2 modes of operation: Precharge and Evaluate. Advantages of dynamic logic circuits: 1) The number of…

VLSI Circuits, VLSI Technology