Flip-Flop (FF) and Latch are digital electronic circuits that are used to store information in bits as they have two stable states. One FF or latch can store 1 bit of information. FF is a circuit that can be made to change its state by applying signals to one or more control inputs and will have one or two outputs.
Both latches and FF are the building blocks of sequential circuits (which use memory elements because their output depend both on present inputs as well as past output). There are four types of flip-flops and latches: D (Data or Delay), T (Toggle), SR (Set-Reset) and JK (Jack-Kilby).
One of the most frequent but confusing question that we face during viva and interviews is the difference between a latch and a flip-flop. Now, let’s make the answer easy to understand by tabulating some simple & important differences between latch and Flip-Flop.
|
Flip-Flop |
Latch |
| The state of circuit changes only when the control signal goes from high to low or low to high (i.e. sensitive to signal change only). | Changes state as soon as the input signals change (of course there is some propagation delay). |
| Synchronous | Asynchronous |
| Edge triggered which means that the output of the circuit changes when there is a change in clock pulse (it may be a positive or negative edge of the clock pulse). | Level triggered which means that the output of the circuit depends on the level of the enable signal (either 1 or 0). |
| Built from latches (a FF is like a clocked latch). FF is used as a register. | Built from logic gates. |
| Works on clock pulses | Works on enable function input |
| Has a clock signal | Does not have a clock signal |
| Edge sensitive i.e. content of FF change only either at the rising or falling edge of the enable signal (usually the controlling clock signal). After the rising or falling edge of the clock signal, the content of FF remains constant even if the input changes. | Level sensitive i.e. content of latch changes immediately when there is a change in its inputs. Output is sensitive for the duration of enable signal active pulse and thus, can transmit or receive data during the active pulse only. |
| Sampling of the inputs is done only at a clock event for example, rising edge, falling edge. | Sampling of the inputs is done continuously only when the enable signal is on. |
Hope the above points would now help you to clearly differentiate between a latch and a flip-flop.
Sir, one question
what does low power design mean in VLSI, what is its importance, because my project is low power bandgap design using cadence tool.
Dear Bipul,
Low power design is one of the major design constraint in VLSI field. For an example, we want a mobile whose battery life is good. A battery life can be good when your circuit consumes low power. So, low power VLSI circuit design is a must for portable devices. Even if for non portable devices it is important, as high power consumption leads to high heat dissipation which in turn can burn out the circuit and can be a cause for fire hazard. So, low power VLSI design is must.
Static Power (power consumed during switched condition – important in low technology node) and Dynamic Power (power consumed during active condition) are the two major components of total power. So, you need to incorporate leakage power reduction scheme to reduce static power consumption and switching power reduction schemes to deal with dynamic power.
Formative but many points are repeated in different words, so to summarize its 3 difference mainly.
what is setup and hold time?
if it gets violated then what happens
Dear bipul,
Setup and hold time are parameters related to flipflops. Violation of setup time and hold time requirement would generate erroneous functional output. In other words in case of violation, flip-flop would generate faulty output.
Setup time is the minimum time required for the data input to be present at the input of the flip-flop before the arrival of the sensitive edge of the clock.
Hold time is the minimum time required for the data input to be present at the input of the flip-flop after the arrival of the sensitive edge of the clock.
Thanks for your response
Happy new year
Actually am doing project in cadence. it’s my b.tech project. Low power bandgap design .
I want some material on analysis Part. That is how to do Monte Carlo analysis, noise analysis, stability analysis and different analysis.
May you help in this regard.
Thank you sir