Taking forward our journey of Interview Question Banks, the next stop is Cypress Semiconductor. Based in United States of America, it is a semiconductor design and manufacturing company. To help you prepare for Cypress and similar companies in similar domain, let’s look at some of the interview questions asked in recent times…
Q : What do you mean by slack?
A : Slack is the amount of time that is measured from when an event ‘actually happens’ and when it ‘should happen’. In simple terms, it is the time gap between predicted time and actual happening time of an event.
Slack = Tactual – Tpredicted
If the slack is negative, it implies timing violation.
Q : What are the uses of buffer?
A : Buffers can be used to introduce small delays in a circuit. They can also be used to support high fan-out and to eliminate crosstalk caused by inter-electrode capacitance due to close routing.
Q : What is phase-shift oscillator?
A : Phase-shift oscillator is a linear electronic oscillator circuit that consists of an inverting amplifying element (like op-amp or transistor) and produces sine wave as output. It has a positive feedback circuit of resistors and capacitors connected in a ladder network which shifts the phase of the circuit by 180 degrees. It is often used in audio applications.
Q : What will happen if there is setup time and hold time violation?
A : Whenever there are setup and hold time violations in any flip-flop, it enters a state known as meta-stable state or quasi-stable state. In this state, the output becomes unpredictable. At the end of meta-stable state, the flip-flop settles down to either logic ‘1’ or ‘0’. This entire process is known as meta-stability.
Q : What is the difference between one-hot and binary encoding FSM design styles?
A : A binary-encoded FSM design requires as many flip-flops as needed to uniquely encode the number of states in the state machine. In this,
number of flip-flops required = ceiling of [log2 (number of states in the FSM)].
A one-hot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or “hot” state) is set at a time in a one hot FSM design. The combinational logic required to implement a one-hot FSM design is typically smaller than most binary encoding styles. Also, one-hot FSMs typically run faster than binary encoded FSM (because these have larger combinational logic blocks).
Q : In digital CMOS design, why do we design the size of PMOS to be higher than the NMOS?
A : In PMOS, holes are the majority carriers whose mobility is less than the electrons (the majority carriers in NMOS). This means that PMOS is slower than NMOS. In CMOS technology, PMOS helps in pulling up the output to VDD (thus known as pull-up network) whereas NMOS helps in pulling down the output to ground (thus called pull-down network). If the sizes of PMOS and NMOS are same, then PMOS takes long time to charge up the output node. But, if we have a larger PMOS, there will be more carriers to charge the node quickly and overcome the slow nature of PMOS. So, to get equal rise and fall times for the output node, size of PMOS is made higher than that of NMOS.
(Continued to Part 2…)
Gautam Vashisht
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