Let's Program the Transistors
This part of the Interview Question Bank deals with the general transistor level questions asked in various VLSI companies Q1. If you connect the input of an inverter to its output where will the output gets settled? Ans. The output will settle at the logical threshold of the inverter ideally at VDD/2. Q2. The Vt…
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Continuing with our series of Question Banks of various core companies of ECE, we have now collected the following questions asked in interviews of Cisco Systems. These questions will help you prepare for on-campus and off-campus interviews of Cisco. Let’s take a look at them… Q : What is gateway? A : Gateway is a…
Read More “Cisco Systems Interview Question Bank – Part 1” »
Qualcomm Interview Question Bank continued from Part 3… Q : What is race-around condition? What is the solution for it? A : In JK flip-flop, when both J and K are 1, the state (output) of the flip-flop will oscillate between 0 and 1 resulting to uncertainty in the state of the flip-flop at the…
Qualcomm Interview Question Bank continued from Part 2… Q : What is the difference between latch and flip-flop? A : The main differences between latch and flip-flop can be understood here. Q : What is the Nyquist rate condition and condition for no aliasing to take place? A : If a signal is bandlimited to W…
Qualcomm Interview Question Bank continued from Part 1… Q : Draw the circuit diagram for a random number generator. A : Following are the circuits for a random number generator (RNG), (i) using IC 555 timer, IC 4026 and 7-segment, (ii) using 8051 and 7-segment, Q : What are the advantages and disadvantage of IIR and…
In the campus placement season, it is better if we get company specific questions to prepare for the selection process. So, to help you out, we have already posted Question Banks for some core ECE companies and now, let us look at the following questions asked in recent times in Qualcomm interviews. In general, according…
Texas Instruments Question Bank continued from Part 1 Q. Draw 2:1 Mux using pass transistors. Ans: Two pass transistors are required to design 2:1 Mux. Q. Draw 2:1 Mux using transmission gates. Ans: Two transmission gates are required to design 2:1 Mux. Q. What is setup and hold time? Ans: Setup time is the minimum amount of time that an input signal…
Q. Implement a 3 bit asynchronous counter using T flip flops. Ans: To design 3 bit asynchronous counter we require 3 T flip flops. Q. What is the always block used for in Verilog? Ans: An always blocks runs continuously throughout the simulation. An always block can be made sensitive to one or more signals depending on the…
Bharat Electronics Limited (BEL) Question Bank continued from Part 4… Q-29. If the gain of the amplifier is A and voltage feedback is fraction B of the amplifier output voltage, what will be the condition for maintenance of oscillation? A : The condition for maintenance of oscillation would be AB = 1. Q-30. State the condition…
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Bharat Electronics Limited (BEL) Question Bank continued from Part 3… Q-20. State a way to improve SNR at the input of an amplifier. A : Signal to Noise Ratio (SNR) at the input of an amplifier can be improved by decreasing the source impedance (or resistance). Q-21. Why are N channel FETs superior to P channel…
Read More “Bharat Electronics Limited (BEL) Question Bank – Part 4” »