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Digital Hardware Design
The TLM 2.0 transaction level modeling standard from the Open SystemC Initiative (OSCI) was released on 9th June 2008. Transaction-level modeling (TLM) is a high-level modern approach to modeling digital systems. That modeling is based on the abstraction of the communications between different parts of the model to allow to work the algorithms of each…
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Transaction-level modeling (TLM) is a high-level modern approach for modeling digital systems. TLM-1 standard defined a set of interfaces which could be used for transporting transaction by value or reference. TLM-1 is being used successfully in some applications but it had shortcomings which have now been improved upon in TLM 2.0. TLM-1 has no standard…
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Setup and Hold time concept is one of the fundamental concepts that is very necessary for closing and analysing and timing margin. The analysis in digital domain, in Reg to Reg system is very popular but the root cause of Setup and Hold time is often not taken care of in the education system. This…
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There are Two types of Procedural Assignments in Verilog. To learn more about Delay: Read Delay in Assignment (#) in Verilog Blocking assignments Example: Non-Blocking assignments Example: To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments The following example shows interactions between blocking and non-blocking for simulation only (not…
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Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment delay: variable = #Δt expression; // “expression” gets evaluated at time 0 but gets assigned to the “variable”…
Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. The following example illustrates the Blocking Assignment Wave forms for the above exampleThe following example illustrates the Non-Blocking Assignment Wave forms for the above example…
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FPGA stands for Field Programmable Gate Array. They are programmable integrated circuits made up of a large number configurable logic blocks (CLBs), fixed function blocks and memory blocks which can be used to perform complex digital computations. The CLBs are the basic and most important unit of FPGA. CLBs are made up of Look Up…
There are two basic types of digital design methodologies: top-down Design Methodology In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided. bottom-up Design Methodology…
Port mapping in module instantiation can be done in two different ways: In this post, we would take one example to understand both types of port mapping in detail. The above Figure shows an example for module instantiation. Figure shows module “SYNCHRO” which consists of 2 ‘D’ flip-flops and are connected in serial fashion. Module “SYNCHRO”…
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A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. Each…