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Digital Hardware Design
In Electronics industry incorrectness in products are described in several ways which may create confusion in understanding the terms defect, error and fault. Though these terms are used interchangeably in the field of VLSI testing, let’s try to draw a fine boundary between the meaning of these terms. Before doing this, we should understand why…
In the previous post we have understood the need of Fault Tolerance in VLSI System Design. A VLSI system can broadly be considered as a union of following 3 layers: Designers introduce several techniques to all these system layers to deal with transient as well as permanent faults, and these techniques incorporate the concept of…
In recent few years VLSI design has achieved remarkable growth. High performance (peta-scale) computing is a reality now and we are expecting exa-scale computing by 2020. We talk about many core processor now a days. Intel’s Xeon Phi (Knights Landing) with 72 cores and IBM’s Kilocore processors with more than 1000 cores are great examples…
The Electronics engineers should know the steps to design a particular circuit. While we study, we directly study the properties of the electronic block and the circuit diagram of the corresponding block. We never think how had we landed up to that particular circuit diagram. For example when we talk about digital Multiplexer, Decoder or Counters; we…
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The TLM 2.0 transaction level modeling standard from the Open SystemC Initiative (OSCI) was released on 9th June 2008. Transaction-level modeling (TLM) is a high-level modern approach to modeling digital systems. That modeling is based on the abstraction of the communications between different parts of the model to allow to work the algorithms of each…
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Transaction-level modeling (TLM) is a high-level modern approach for modeling digital systems. TLM-1 standard defined a set of interfaces which could be used for transporting transaction by value or reference. TLM-1 is being used successfully in some applications but it had shortcomings which have now been improved upon in TLM 2.0. TLM-1 has no standard…
Read More “What is TLM-1 and what was the need for TLM 2.0?” »
Setup and Hold time concept is one of the fundamental concepts that is very necessary for closing and analysing and timing margin. The analysis in digital domain, in Reg to Reg system is very popular but the root cause of Setup and Hold time is often not taken care of in the education system. This…
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There are Two types of Procedural Assignments in Verilog. To learn more about Delay: Read Delay in Assignment (#) in Verilog Blocking assignments Example: Non-Blocking assignments Example: To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments The following example shows interactions between blocking and non-blocking for simulation only (not…
Read More “Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog” »
Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment delay: variable = #Δt expression; // “expression” gets evaluated at time 0 but gets assigned to the “variable”…
Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. The following example illustrates the Blocking Assignment Wave forms for the above exampleThe following example illustrates the Non-Blocking Assignment Wave forms for the above example…
Read More “Synthesis and Functioning of Blocking and Non-Blocking Assignments.” »