Author: vlsifacts

Conference Deadlines – VLSI and Computer Architecture in India – 2018

February 23, 2018June 17, 2025 vlsifacts No Comments

Following list updates the deadlines of the conferences in the domain of VLSI and Computer Architecture to be held in India for the year 2018-19. You can find the list of conferences by clicking here. 32nd International Conference on VLSI Design & 18th International Conference on Embedded Systems (VLSID – 2019) Date of Conference: TBA Place of…

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VLSI and Computer Architecture Conferences in India

January 27, 2018June 17, 2025 vlsifacts 2 Comments

The following list contains the VLSI and Computer Architecture conferences which are held in India every year. The table holds the list of conferences which is at least 3 years old. This list is meant to hold the conferences whose major tracks are either one or multiple of the following categories: Device – Circuit Interactions…

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Reliability vs. Availability in Fault Tolerance

January 3, 2018June 17, 2025 vlsifacts No Comments

We have learnt the following definitions of Reliability and Availability from the Fault Tolerance Measures post: Reliability, R(t): Probability that the system has been up continuously during the whole interval [0,t], given it was up at time 0. This measure is suitable for applications in which even a momentary disruption can prove costly. One example is computer…

Fault Tolerant System Design

Fault Tolerance Measures

November 16, 2017June 17, 2025 vlsifacts No Comments

Fault tolerance of electronic system is a major concern for the VLSI engineers. This can be realized from the post Need of Fault Tolerant VLSI System Design. The objective of this post is to introduce the proper tools for fault tolerance measure. A measure is a mathematical abstraction, which expresses only some subset of the object’s…

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Fault Tolerant System Design

Defects, Errors, and Faults

November 13, 2017June 17, 2025 vlsifacts No Comments

In Electronics industry incorrectness in products are described in several ways which may create confusion in understanding the terms defect, error and fault. Though these terms are used interchangeably in the field of VLSI testing, let’s try to draw a fine boundary between the meaning of these terms. Before doing this, we should understand why…

Fault Tolerant System Design

Redundancy in Fault Tolerance

November 5, 2017July 1, 2025 vlsifacts No Comments

In the previous post we have understood the need of Fault Tolerance in VLSI System Design. A VLSI system can broadly be considered as a union of following 3 layers: Designers introduce several techniques to all these system layers to deal with transient as well as permanent faults, and these techniques incorporate the concept of…

Fault Tolerant System Design

Need of Fault Tolerant VLSI System Design

October 28, 2017June 17, 2025 vlsifacts No Comments

In recent few years VLSI design has achieved remarkable growth. High performance (peta-scale) computing is a reality now and we are expecting exa-scale computing by 2020. We talk about many core processor now a days. Intel’s Xeon Phi (Knights Landing) with 72 cores and IBM’s Kilocore processors with more than 1000 cores are great examples…

Fault Tolerant System Design

Interview Experience – Qualcomm (On Campus – #2)

July 20, 2017June 17, 2025 vlsifacts No Comments

This is an interview experience of Qualcomm, an American multinational semiconductor and telecommunications equipment company. This is an on campus placement experience and has been share by Mr. Ishaind Gupta (IIIT Delhi). As we all know that in this every second changing world a smart phone plays a very big role. A smartphone enables a…

Interview Experience

MEMS Design Contest 2018 in association with Cadence Academic Network, X-FAB, Coventor, and Reutlingen University

September 6, 2016June 17, 2025 vlsifacts No Comments

A world wide MEMS (Microelectromechanical systems) Design Contest is going to be organized in 2017-18. The Cadence Academic Network, X-FAB, Coventor, and Reutlingen University have been teamed up to build this platform which would provide the opportunity to showcase the innovative ideas. The contest is all about design and build the best MEMS and mixed-signal designs. Important Timeline December…

MEMS, Notifications

India Innovation Challenge with support from Texas Instruments India, DST and IIMB

September 5, 2016June 17, 2025 vlsifacts No Comments

Texas Instruments Inc. in collaboration with Department of Science and Technology(DST) proudly announce the ‘DST & Texas Instruments Inc. India Innovation Challenge Design Contest 2016′, Anchored by the Indian Institute of Management (IIM), Bangalore and supported by MyGov. The contest is open for all students pursuing B.E./B.Tech,M.E./M.Tech & Ph.D from Indian engineering colleges. This challenge…

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