Let's Program the Transistors
A “module” is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. Module interface refers, how module communicates with external world. This communication…
The states which are equivalent, are redundant. Because by looking at the output, we can not even figure out in which state the machine is in. So, if there are two equivalent states then there is no point of using both the states. We can merge both the states and can use only one state….
Sometimes a state diagram constructed for a finite state machine contains redundant states, i.e. states whose function can be accomplished by other states. The number of memory elements required for the realization of a machine is directly related to the number of states. Consequently, the minimization of the number of states does reduce the complexity…
This post illustrates the circuit design of Even Parity Generator. State Machine diagram for the same Parity Generator has been shown below. Click here to realize how we reach to the following state transition diagram. Click here to learn the step by step procedure of “How to synthesize a state machine / How to boil down…
Parity generator can be of two types: (i) Even Parity Generator (ii) Odd Parity Generator In this post we will derive the state machine for an even parity generator. Consider input “I” is a stream of binary bits. When an input comes, the even parity generator checks whether the total number of 1’s received till…
This post illustrates the circuit design of Sequence Detector for the pattern “1101”. State Machine diagram for the same Sequence Detector has been shown below. Click here to realize how we reach to the following state transition diagram. Click here to learn the step by step procedure of “How to synthesize a state machine / How…
Sequence Detector is a digital system which can detect/recognize a specified pattern from a stream of input bits. Let’s say the Sequence Detector is designed to recognize a pattern “1101”. Consider input “X” is a stream of binary bits. When the Sequence Detectors finds consecutive 4 bits of input bit stream as “1101”, then the…
Read More “State Machine Diagram for Pattern Recognition / Sequence Detector” »
State machine synthesis is a process of of boiling down a state machine to a digital logic circuit. Steps in State Machine Synthesis Let’s achieve the state machine realization of the following state diagram Let’s assume that we have completed the first two steps mentioned above and achieved a minimized Mealy state machine as shown…
Flipflops to be considered are: SR Flipflop S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Invalid inputs Characteristic Equation Q(t+1) = R'(t)Q(t) + S(t) ; S(t)R(t) = 0 Excitation Table Q(t) Q(t+1) S R 0 0 0 x 0 1 1 0 1 0 0 1 1 1 x…
Read More “Truth Tables, Characteristic Equations and Excitation Tables of Different Flipflops” »
Sequential machines can be designed in two different ways: (i) Mealy Machine & (ii) Moore Machine Considering Mealy or Moore for the designing of sequential machine, it’s actually difficult to draw a hard line where one machine is always better than the other. Depending on the application requirement one may dominate the other. It is…
Read More “Mealy to Moore and Moore to Mealy Transformation” »