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Author: vlsifacts

What is Post-Silicon Validation

Posted on November 28, 2019June 18, 2025 By vlsifacts No Comments on What is Post-Silicon Validation

Modern day Syetem-on-Chips are so complex that pre-silicon verification is no more the sufficient step to capture all the design bugs. Even with sophisticated verification process, achieving 100% coverage is difficult. Due to this, few bugs escape from the pre-silicon verification till the actual product on silicon. So, now-a-days industries perform post-silicon validation (commonly known…

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DHD, Verification

Pre-Silicon Verification vs. Post-Silicon Validation

Posted on November 19, 2019June 17, 2025 By vlsifacts No Comments on Pre-Silicon Verification vs. Post-Silicon Validation

Both Verification and Validation checks for the correctness of the design. These design steps try to detect and localize functional bugs in the system. While pre-silicon verification runs the test cases on the software prototypes of the design on the simulator, post-silicon validation is executed on a few initial hardware prototypes of the design on…

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DHD, Verification, VLSI Testing

Resistive Divider Circuit

Posted on November 8, 2018June 17, 2025 By vlsifacts No Comments on Resistive Divider Circuit

Resistive divider circuit can alternatively be called as voltage divider circuit. Such a circuit is shown in the following figure: This circuit divides the input voltage Vin depending on the resistance values according to the following formula: Vout = Vin x (R2/(R1 + R2)) Vout is the output voltage, which is nothing but the voltage…

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Electric

Resistive Divider Layout Simulation

Posted on November 8, 2018June 17, 2025 By vlsifacts No Comments on Resistive Divider Layout Simulation

Now we are ready to simulate the layout view off this cell. Let’s open up the schematic view of the cell and copy the SPICE code. Go back to the layout view and paste the SPICE code. Increase the text size of the spice code to 10 by going to its object property (Ctrl+I). The…

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Electric

Resistive Divider Layout

Posted on November 8, 2018June 17, 2025 By vlsifacts No Comments on Resistive Divider Layout

Open the layout view of the Resistive_divider cell and then copy/paste (Ctrl+C/Ctrl+V) an additional resistor. Running a DRC (pressing F5) on the above layout results in the following error. By pressing > we see that there is too little space between the N-wells. Move the Nodes apart until the layout passes the DRCs. Of-course the…

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Electric

Resistive Divider Schematic Simulation

Posted on November 7, 2018June 17, 2025 By vlsifacts No Comments on Resistive Divider Schematic Simulation

Now we would simulate the resistive divider circuit which has been built, and would observe the output voltage w.r.t. a particular input voltage. For this we need to write a SPICE code which would give the description of the input voltage and would indicate the type of simulation we want to perform. Writing SPICE Code…

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Electric

Resistive Divider Schematic

Posted on November 7, 2018June 17, 2025 By vlsifacts No Comments on Resistive Divider Schematic

Before starting the schematic design let’s celebrate the fact that the most commonly used following shortcuts in our daily life are also valid for Electric VLSI. Now we would build a resistive divider circuit. Go to the schematic view of the Resistive_divider cell. Select the N-Well resistor Node and then copy the same by pressing Ctrl+C….

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Electric

Setup of LTspice with Electric

Posted on November 7, 2018June 17, 2025 By vlsifacts 3 Comments on Setup of LTspice with Electric

LTspice is a free software which performs SPICE simulations for electronic circuits. We use LTspice for spice simulation of the circuit designed in Electric. Setting in Electric Following are the steps to be followed to set up LTspice with Electric: Ensure LTspice is installed on your computer. Go to File –> Preferences –> Categories –>…

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Electric

Checking ERC (Well Check)

Posted on November 6, 2018June 17, 2025 By vlsifacts No Comments on Checking ERC (Well Check)

This process checks the connection of the n-well and p-substrate. The C5 process used here is an n-well process. The p-type substrate is common to all NMOS devices and should be grounded. One of the electrical rule checks (ERCs) is to verify that the p-well (in this case p-substrate) is always connected to ground. Further,…

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Electric

Layout vs. Schematic (LVS)

Posted on November 6, 2018June 17, 2025 By vlsifacts 1 Comment on Layout vs. Schematic (LVS)

Layout vs. Schematic (LVS) in Electric is checked using Network Consistency Checking (NCC) To check this, execute Tools –> NCC –> Schematic and Layout views of Cell in Current Window. You can run this command being in any design window (schematic / layout). We can execute the above command by only pressing ‘L‘ as we have…

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Electric

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