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Author: Jitendra

ESD Models and their comparison – ESD Part 2

Posted on January 26, 2018June 17, 2025 By Jitendra No Comments on ESD Models and their comparison – ESD Part 2

In the part-1 of ESD we learnt through of ESD testing and its importance. ICs are susceptible to ESD event as they consist of components that are very sensitive to excess current and voltage. ESD even can occur at any point in time during IC assembly and packaging, part handling or system assembly. Important point…

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VLSI Circuits, VLSI Technology

Electro-Static Discharge (ESD) – VLSI Circuit’s Prospective

Posted on January 15, 2018June 17, 2025 By Jitendra No Comments on Electro-Static Discharge (ESD) – VLSI Circuit’s Prospective

Electro Static Discharge (ESD) is sudden flow of static electricity between two electrically charged objects for a very short duration of time. The study of ESD phenomenon and its protection circuits are more relevant with each technology nodes as smaller devices are more vulnerable. Electric Over-Stress (EOS) is also one by-product of ESD which also…

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VLSI Circuits

The Mystery of Monte Carlo Simulation

Posted on October 1, 2016June 17, 2025 By Jitendra No Comments on The Mystery of Monte Carlo Simulation

If you are in VLSI industry, sometime or the other, you must have heard this term “Mont Carlo (MC)”. In this post let us understand the literal meaning of Monte Carlo simulation and its application in circuit design field. Going by the wiki definition of Monte Carlo “Monte Carlo methods are a broad class of computational…

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VLSI Circuits, VLSI Technology

Interview Experience – Texas Instruments (Off Campus)

Posted on May 6, 2016June 17, 2025 By Jitendra 2 Comments on Interview Experience – Texas Instruments (Off Campus)

This is my interview experience with Texas Instruments India. I was searching for job in circuit design field and what could be a better opportunity than TI. I applied to TI on their career site (as most of us do), but apparently received NO response. Then I started connecting to people who are working in…

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Interview, Interview Experience

PMOS is no longer the Culprit

Posted on March 23, 2016June 17, 2025 By Jitendra No Comments on PMOS is no longer the Culprit

MOS scaling has introduced many undesired effects, known second order ones being channel length modulation, velocity saturation, mobility degradation etc. These are introducing a new set of challenges for the designers. From the performance perspective, supply voltage scaling has reduced the driving capability of MOS due to decrease in effective overdrive voltage. On the other…

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Fabrication, VLSI Technology

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