Many of you might have worked on different VLSI technology nodes such as 180 nm, 90 nm, 45 nm etc. in circuit simulation tools like Cadence etc. With the invention and evolution of transistors, various technologies came into existence and more would continue to come in future. According to Moore’s law, the number of transistors will continue to double in every 1.5 years. That means the same silicon area would accommodate more and more number of transistors. To achieve this, transistor size is gradually getting reduced. This we say, transistor size is shifting from one technology node to a smaller technology node by scaling process.The sifting of technology node helped many leading players in semiconductor industry like Intel, IBM, AMD, Texas Instruments etc. to come up with many innovative and highly powerful products day by day. A particular technology gets used by the industries for a span of time period till the time the next feasible smaller technology node would be ready for implementation. For example, 180 nm technology was used by most of them in the 1999-2000 time-frame, while 90 nm was used in 2004-2005.
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Seeing the above technological evolution and having worked on them, have you ever tried to find the answer of a question that what is the difference between these different technologies used in VLSI?
Starting with the main difference between the technologies – 180 nm, 90 nm etc., the numbers represent the minimum feature size of the transistor (PMOS or NMOS). The minimum feature size means that during the fabrication process of a transistor, how closely can the transistors be placed on a chip to be used for various purposes. The smaller this size is, the larger number of transistors can be fabricated on the chip. For example, suppose separate chips are to be designed using 180 nm and 90 nm transistors. Now, the number of 90 nm transistors that can be placed on a particular area of the chip would be more (nearly twice) than the number of 180 nm ones that can be placed on the same silicon area.
The above can also be understood by the fact that the numbers 180 nm, 90 nm etc. represent the minimum channel length that can be used in fabrication. Also, these numbers aren’t randomly assigned but decided by dividing the previous number by square root of 2 (2 because it is neither too small nor too big). For example, the next technology node after 180 nm was 180 divided by square root of 2 which comes out to be nearly 130 nm. Likewise, the next after 130 nm will be 130 divided by square root of 2 which is approximately 90 nm and so on. Different technologies are being used today and the transistor size is shrinking day-by-day to lower the cost of production of a chip as smaller the chip, cheaper is to make it. In the year 2016, the technology will come down to be around 11 nm and estimated to be 4 nm (approx.) by the year 2020!.
sir, may I know, what is the advantage of low power in VLSI design
Dear Bipul,
Low power in VLSI is considered as an important parameter and taken as a design constraint. In earlier days when electronic devices were only table top then power was not considered as a design constraint because the device could be connected to the power supply all the day. But when portable devices like mobile phone, laptop etc. came into market then power became important. The devices are desired to consume less power, so that it can run for a longer time. That is why low power VLSI design is important. Also high power consuming devices dissipates more heat, so there is a chance of thermal hotspot which can lead to burning of the chip. This also makes low power design important.
Sir, according to Moore’s law, every 1.5 years the technology changes and the size is reducing from 180 nm to 90 nm and so on… to ~7nm now(2018)
If this continues, after reaching a particular level(size of the atom), it may not be possible to reduce the size further. So, can we consider it as a end for the research in chip compaction??
Dear Yashwanth,
It’s true that the technology is scaling generation to generation, though today Moore’s law is not followed strictly. But the chip compaction research will never come to an end. You can find people come with new research for new materials in semiconductor industry. People also come with new technologies like FINFET and FDSOI. So, keeping in mind, the market growth of embedded system industry in the world, the research will never stop, and something new would definitely come from generation to generation.
Sir, can digital logic gates or circuits designed in 180nm technology in Cadence Virtuoso be used in 90nm technology ?
No Aditya, you can’t use a circuit in a particular technology which is designed using another technology node.
sir, can I know what are the differences that we do observe during the design of 90nm and 28nm technology projects (synthesis & PNR)
Dear Tejaswini,
After synthesis, you can observe lower area consumption in case of 28nm than 90nm.
Hello Sir,
we have noticed that , suppose we are working on 28nm technology node, the channel length given in the netlist to draw the layout is 40nm. none of the transistor size in the particular block was 28nm. Can you please explain why this is done?
What’s the main differences we can notice when we switch from 28nm to 7nm in terms of timing, area and other aspects. Can you please explain??