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Tag: VHDL

Case and Conditional Statements Synthesis CAUTION !!!

Posted on November 12, 2015June 16, 2025 By Priyadarshi 5 Comments on Case and Conditional Statements Synthesis CAUTION !!!

Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by programming its functionality. Let’s say, we have to design a circuit that selects a particular…

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DHD, Digital Electronics, Verilog

Interview Experience – Tech Mahindra – VLSI Domain (Off Campus – Telephonic)

Posted on October 26, 2015May 18, 2025 By Priyadarshi 2 Comments on Interview Experience – Tech Mahindra – VLSI Domain (Off Campus – Telephonic)

I got an Interview call from Tech Mahindra VLSI Dept, and I am sharing my Interview Experience here. The Interview was telephonic and and was about 55 minutes long. They asked for core technical questions related to HDL (Hardware Description Language) which you can answer correctly only if you have some basic work experience with…

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Interview Experience

Interview Experience – Silicon Interfaces – for Trainee VLSI Design (Off Campus)

Posted on August 28, 2015May 18, 2025 By Priyadarshi No Comments on Interview Experience – Silicon Interfaces – for Trainee VLSI Design (Off Campus)

Hello everyone !!!This is my interview experience for the post of Trainee VLSI design at Silicon Interfaces, A software and VLSI Design centre. This post also presents my thoughts towards “What should be done to get noticed by VLSI companies“. This article would be of great assistance to those, who are vouching to make a…

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Interview Experience

Verilog vs VHDL

Posted on July 20, 2015June 23, 2025 By Dewansh No Comments on Verilog vs VHDL

Verilog and VHDL are Hardware Description languages (HDL) that are used to describe the behavior and structure of electronic systems. HDL languages are different form software language like ‘C’, as they use concurrency constructs to simulate circuit behavior. HDL includes a means of describing propagation time and signal strength. Verilog Vs. VHDL

DHD, Verilog, VHDL

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