Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by…
Tag: VHDL
Interview Experience – Tech Mahindra – VLSI Domain (Off Campus – Telephonic)
I got an Interview call from Tech Mahindra VLSI Dept, and I am sharing my Interview Experience here. The Interview was telephonic and and was about 55 minutes long. They asked for core technical questions related to HDL (Hardware Description…
Interview Experience – Silicon Interfaces – for Trainee VLSI Design (Off Campus)
Hello everyone !!! This is my interview experience for the post of Trainee VLSI design at Silicon Interfaces, A software and VLSI Design centre. This post also presents my thoughts towards “What should be done to get noticed by VLSI…
Verilog vs VHDL
Verilog and VHDL are Hardware Description languages (HDL) that are used to describe the behavior and structure of electronic systems. HDL languages are different form software language like ‘C’, as they use concurrency constructs to simulate circuit behavior. HDL includes…