Let's Program the Transistors
A “module” is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. Module interface refers, how module communicates with external world. This communication…
This post contains some very interesting interview questions asked by Synopsys the EDA giant in its interview. The questions are based on Verilog Synthesis and Simulation. Though I have included the answers; I would encourage the reader to experiment himself or herself and then discuss these in the forum. 1. How a latch gets inferred…
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Hello Everyone! This is my training experience, I had at Mentor Graphics, Noida (Higher Education Program) which is conducted annually for pre-final year B.Tech and M.Tech students. It is a two month training program that starts in June and lasts till the last week of July. The main aim of the training is “Verification of…
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Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by programming its functionality. Let’s say, we have to design a circuit that selects a particular…
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I got an Interview call from Tech Mahindra VLSI Dept, and I am sharing my Interview Experience here. The Interview was telephonic and and was about 55 minutes long. They asked for core technical questions related to HDL (Hardware Description Language) which you can answer correctly only if you have some basic work experience with…
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Hello everyone !!!This is my interview experience for the post of Trainee VLSI design at Silicon Interfaces, A software and VLSI Design centre. This post also presents my thoughts towards “What should be done to get noticed by VLSI companies“. This article would be of great assistance to those, who are vouching to make a…
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These are some simple steps which can be used to do the power analysis of a design using Xpower Analyzer which comes readily available in the ISE free web pack. ## Make sure your circuit can be synthesized. Then under the implement design option in the project navigator, Place and Route the design. ## The…
Verilog and VHDL are Hardware Description languages (HDL) that are used to describe the behavior and structure of electronic systems. HDL languages are different form software language like ‘C’, as they use concurrency constructs to simulate circuit behavior. HDL includes a means of describing propagation time and signal strength. Verilog Vs. VHDL