Tag: Simulation

Compilation, Elaboration, and Simulation in HDL: A Clear Guide with Examples

July 21, 2025July 18, 2025 vlsifacts No Comments

When working with Hardware Description Languages (HDLs) such as Verilog or VHDL, understanding the design flow is crucial for successful digital circuit development. Three fundamental steps in this flow are Compilation, Elaboration, and Simulation. These steps ensure that your HDL code is syntactically correct, logically consistent, and behaves as expected before hardware implementation. In this article, we will…

Verification, Verilog

Intermediate Verilog Questions for Designers (Part – 2) : Strengthen Your Coding and Design Skills

July 4, 2025July 18, 2025 vlsifacts No Comments

1. What is the difference between synthesis and simulation? 2. How to prevent race conditions in simulations? 3. Difference between ifdef and ifndef? Example of ifdef: Example of ifndef: ifdef and ifndef directives help control conditional compilation, enabling flexible and reusable code for different environments such as simulation, synthesis, debugging, or different target platforms. 4. What is…

Interview, Question Bank, Verilog

Setup of LTspice with Electric

November 7, 2018June 17, 2025 vlsifacts 3 Comments

LTspice is a free software which performs SPICE simulations for electronic circuits. We use LTspice for spice simulation of the circuit designed in Electric. Setting in Electric Following are the steps to be followed to set up LTspice with Electric: Ensure LTspice is installed on your computer. Go to File –> Preferences –> Categories –>…

Electric

Synopsys – Interview Questions – based on Synthesis and Simulation

January 19, 2016June 16, 2025 Priyadarshi No Comments

This post contains some very interesting interview questions asked by Synopsys the EDA giant in its interview. The questions are based on Verilog Synthesis and Simulation. Though I have included the answers; I would encourage the reader to experiment himself or herself and then discuss these in the forum. 1. How a latch gets inferred…

DHD, Digital Electronics, Interview, Interview Experience, Verilog