Skip to content

VLSIFacts

Let's Program the Transistors

  • Home
  • DHD
    • Digital Electronics
    • Fault Tolerant System Design
    • TLM
    • Verification
    • Verilog
    • VHDL
    • Xilinx
  • Embedded System
    • 8085 uP
    • 8086 uP
    • 8051 uC
  • VLSI Technology
    • Analog Electronics
    • Memory Devices
    • VLSI Circuits
  • Interview
    • Interview Experience
    • Training Experience
    • Question Bank
  • Notifications
  • QUIZ
  • Community
  • Job Board
  • Contact Us
  • Toggle search form

Tag: Quartus

Case and Conditional Statements Synthesis CAUTION !!!

Posted on November 12, 2015June 16, 2025 By Priyadarshi 5 Comments on Case and Conditional Statements Synthesis CAUTION !!!

Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by programming its functionality. Let’s say, we have to design a circuit that selects a particular…

Read More “Case and Conditional Statements Synthesis CAUTION !!!” »

DHD, Digital Electronics, Verilog

Top Posts & Pages

  • ASCII Code
  • Circuit Design of a 4-bit Binary Counter Using D Flip-flops
  • Truth Tables, Characteristic Equations and Excitation Tables of Different Flipflops
  • NAND and NOR gate using CMOS Technology
  • AND and OR gate using CMOS Technology


 

Copyright © 2025 VLSIFacts.

Powered by PressBook WordPress theme