Skip to content

VLSIFacts

Let's Program the Transistors

  • Home
  • DHD
    • Digital Electronics
    • Fault Tolerant System Design
    • TLM
    • Verification
    • Verilog
    • VHDL
    • Xilinx
  • Embedded System
    • 8085 uP
    • 8086 uP
    • 8051 uC
  • VLSI Technology
    • Analog Electronics
    • Memory Devices
    • VLSI Circuits
  • Interview
    • Interview Experience
    • Training Experience
    • Question Bank
  • Notifications
  • QUIZ
  • Community
  • Job Board
  • Contact Us

Tag: Process induced strained silicon

PMOS is no longer the Culprit

Posted on March 23, 2016June 17, 2025 By Jitendra No Comments on PMOS is no longer the Culprit

MOS scaling has introduced many undesired effects, known second order ones being channel length modulation, velocity saturation, mobility degradation etc. These are introducing a new set of challenges for the designers. From the performance perspective, supply voltage scaling has reduced the driving capability of MOS due to decrease in effective overdrive voltage. On the other…

Read More “PMOS is no longer the Culprit” »

Fabrication, VLSI Technology

Top Posts & Pages

  • ASCII Code
  • Circuit Design of a 4-bit Binary Counter Using D Flip-flops
  • NAND and NOR gate using CMOS Technology
  • AND and OR gate using CMOS Technology
  • Synthesis Constructs in Verilog: A Comprehensive Guide for Designers

Copyright © 2025 VLSIFacts.

Powered by PressBook WordPress theme

Subscribe to Our Newsletter