Tag: CMOS

SETUP Time and SETUP Violation in a Single D Latch

Posted on By Priyadarshi 2 Comments on SETUP Time and SETUP Violation in a Single D Latch

Setup and Hold time concept is one of the fundamental concepts that is very necessary for closing and analysing and timing margin. The analysis in digital domain, in Reg to Reg system is very popular but the root cause of Setup and Hold time is often not taken care of in the education system. This…

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DHD, Digital Electronics, Memory Devices, SoC, VLSI Circuits

Interview Experience – Si2Chip – Memory Design

Posted on By Priyadarshi 2 Comments on Interview Experience – Si2Chip – Memory Design

I want to share my interview experience in Si2Chip, a design and layout based service company in Bangalore. I applied though the career section of the company and got the call for the Memory Design requirement. There were two telephonic technical rounds consisting of quality technical discussion. Most of the discussion revolved around Memory design…

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Interview, Interview Experience, Memory Devices, Question Bank

Advantages and Disadvantages of a Dynamic CMOS Circuit over a Static CMOS Circuit

Posted on By Dewansh No Comments on Advantages and Disadvantages of a Dynamic CMOS Circuit over a Static CMOS Circuit

Static CMOS circuits use complementary nMOS pulldown and pMOS pullup networks to implement logic gates or logic functions in integrated circuits. Dynamic gates use a clocked pMOS pullup. The implemented logic function or the logic gate is achieved through 2 modes of operation: Precharge and Evaluate. Advantages of dynamic logic circuits: 1) The number of…

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VLSI Circuits, VLSI Technology