Search Results for: interview

Interview Experience – WIPRO GMT (Global Media & Telecom ) – (On Campus – #2)

January 13, 2016May 18, 2025 vlsifacts No Comments

I am Jitendra Kumar Yadav, Jaypee Institute of Information Technology. This is my interview experience for the post of Project Engineer at Wipro Limited. I have described my selection process for the mentioned post in the following content. Check here the first post on “Interview Experience – WIPRO Limited – Telecom Domain“ Technical Interview First of all I…

Interview, Interview Experience

Interview Experience – Tech Mahindra – VLSI Domain (Off Campus – Telephonic)

October 26, 2015May 18, 2025 Priyadarshi 2 Comments

I got an Interview call from Tech Mahindra VLSI Dept, and I am sharing my Interview Experience here. The Interview was telephonic and and was about 55 minutes long. They asked for core technical questions related to HDL (Hardware Description Language) which you can answer correctly only if you have some basic work experience with…

Interview Experience

Interview Experience – Aricent Technologies (On Campus)

October 26, 2015June 16, 2025 Gautam No Comments

Hello everyone, this is my interview experience at the on-campus placement drive of Aricent Technologies. Aricent visited our campus on 30th September 2015. Being from the Electronics & Communication Engineering (ECE) branch, I was very much excited about its visit, as it is a core company which deals with “Communications Infrastructure” and “Embedded Systems“. The first…

Interview Experience

Interview Experience – WIPRO Limited – Telecom Domain (On Campus)

October 10, 2015June 16, 2025 Dewansh 2 Comments

This is my interview experience for the post of Associate Telecom Engineer at Wipro Limited. Wipro visited our campus (JIIT Noida) for the first time to hire electronic students for their telecom domain. The selection procedure consisted of four parts: the Aptitude Test, Technical Test, Technical Interview and finally followed by the HR Interview. Round…

Interview Experience

Interview Experience – Silicon Interfaces – for Trainee VLSI Design (Off Campus)

August 28, 2015May 18, 2025 Priyadarshi No Comments

Hello everyone !!!This is my interview experience for the post of Trainee VLSI design at Silicon Interfaces, A software and VLSI Design centre. This post also presents my thoughts towards “What should be done to get noticed by VLSI companies“. This article would be of great assistance to those, who are vouching to make a…

Interview Experience

VLSI ROADMAP (2026 Ready) — From Beginner to Job-Ready

January 25, 2026January 25, 2026 vlsifacts No Comments

This roadmap is created to give aspirants a practical and updated view of the VLSI landscape in 2026 – covering not only mainstream tracks like RTL and UVM, but also specialized and high-growth domains like STA/timing closure, low power, power integrity, DFT/ATPG/BIST, FPGA prototyping & emulation, analog/layout, memory & IO libraries, PDK enablement, and the rising influence of AI/ML and agentic EDA workflows.

VLSI Career

Compilation, Elaboration, and Simulation in HDL: A Clear Guide with Examples

July 21, 2025December 13, 2025 vlsifacts No Comments

When working with Hardware Description Languages (HDLs) such as Verilog or VHDL, understanding the design flow is crucial for successful digital circuit development. Three fundamental steps in this flow are Compilation, Elaboration, and Simulation. These steps ensure that your HDL code is syntactically correct, logically consistent, and behaves as expected before hardware implementation. In this article, we will…

Verification, Verilog

Understanding the 4-bit Ripple Carry Adder: Verilog Design and Testbench Explained

July 20, 2025December 13, 2025 vlsifacts No Comments

In digital electronics and VLSI design, adders are fundamental building blocks used to perform arithmetic operations. Among various types of adders, the 4-bit Ripple Carry Adder (RCA) is one of the simplest and most commonly studied designs. It is widely used to add two 4-bit binary numbers and produce a 4-bit sum along with a carry-out. This…

Digital Electronics, Verilog

Si2Chip (Scheduled Walk in Drive) – Physical Designer – 2019 (Jan)

Si2Chip Job…

Cambio Consulting – ASIC RTL DESIGN Engineer – 2019 (Jan)

Through the Recruitment Consulting Firm Cambio Consulting Job Board Position: ASIC RTL DESIGN Engineer Location: Bangalore Job Type: Full Time Educational Qualification: B. Tech. / M. Tech. in Electronics or equivalent degree Essential Experience in Years: 7 – 15 years Essential Experience in Skills and Expertise: Experience: 7 to 15 tears in ASIC…