Ports in Verilog Module

Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All ports declared as one of the above is assumed to be a wire by default, to declare it otherwise it is necessary to declare it again. For example in the D-type flip flop we want the output to hold on to its value until the next clock edge so it has to be a register.

module d_ff(q,d,reset,clock); // all ports must be declared as input or output
  output q;
  input d, reset, clock;
  reg q; // the ports can be declared again as required

....... 

endmodule

Note: by convention, outputs of the module are always first in the port list. This convention is also used in the predefined modules in Verilog.

A different way ports can be declared as below other than the above one:

module d_ff(
  output reg q,
  input d,reset,clock);

....... 

endmodule