Interview Experience – Tech Mahindra – VLSI Domain (Off Campus – Telephonic)

I got an Interview call from Tech Mahindra VLSI Dept, and I am sharing my Interview Experience here. The Interview was telephonic and and was about 55 minutes long. They asked for core technical questions related to HDL (Hardware Description Language) which you can answer correctly only if you have some basic work experience with front end VLSI.

I received a call from the H.R. dept., Tech Mahindra regarding my application and a time slot has been fixed for the Interview, Their requirement was inclined towards VHDL as I suppose it was the need of their on going projects. I got a call from the technical department at the scheduled time. The panel consisted of two interviewers.

After the formal introduction and inquiry about my current occupation they came to the point straight away and asked me about my knowledge of VHDL. I told that I have worked on it but i would prefer Verilog if given a choice. After that they gave me a test scenario and asked me to write a code to verify that and then recite to them. I asked for permission to do that in Verilog as I am more comfortable in it. They accepted the request, but seemed like not that happily. I wrote what I could and then recited. They pointed out some flaws in that and I racked my brain to correct it. After several attempts I got more closer but not completely correct. Sensing that now they are fidgeting, I politely gave up and tried drawing their attention to the experience I have, which worked and they started asking some good fundamental questions.

The question which was placed by them for me after the test case question was to tell the difference between $monitor and $display and their application. They also asked some tricky things about how many times you can use $monitor etc, for which I replied taking my time.

After that they came to the state machines, asked me about the types, difference, preference for use. I answered promptly to that. Then they asked me to recite the code for both the types of state machines in VHDL, which I did comfortably with an example.

Then they asked me about the Blocking and Non-Blocking assignments in Verilog, for which I replied correctly.

After that they asked me about constants, variables, signals and their difference and synthesis. I answered with examples. One thing which I have realized is that always support your answer with an example if you know it well, this will have a great impact.

Then they came to my projects, asked about my work, and functioning of the projects, by picking projects one by one in the line. They asked about the problems I faced during the projects and basic technical questions related to them. I think mostly they were trying to figure out whether I have really worked on those projects or not.

They ended the Interview then, saying that H.R. manager will contact you, and H.R. manager did inform that I have cleared their Interview, and my application is in consideration 🙂

One think I like to suggest freshers is that do as many projects as you can, this will help in a big way, clearing your concepts and enhancing your skills, also you have a proof that you have actually worked on things. I hope this post will be of use to you and will encourage you to work hard, towards a career in VLSI.

Priyadarshi Saxena