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How to Implement a Priority Encoder in Verilog: Step-by-Step Guide

Posted on July 4, 2025July 2, 2025 By vlsifacts No Comments on How to Implement a Priority Encoder in Verilog: Step-by-Step Guide

In digital design, efficiently managing multiple input signals and prioritizing them is crucial. This is where a priority encoder comes into play. Whether you’re designing interrupt controllers, multiplexers, or resource arbitration logic, understanding how to implement a priority encoder is essential.

In this blog post, we’ll explore what a priority encoder is, why it’s important, and walk through a clear, step-by-step implementation using if-else statements in Verilog. By the end, you’ll have a solid grasp of how to encode the highest-priority active input into a binary output.

What is a Priority Encoder?

A priority encoder is a combinational circuit that takes multiple input lines and outputs the binary code corresponding to the highest-priority active input. Think of it as a smart selector that always chooses the most important signal when multiple inputs are active simultaneously.

For example, if you have four inputs and both the second and fourth inputs are active, the priority encoder will output the code for the fourth input because it has the highest priority.

Why Use a Priority Encoder?

Priority encoders are widely used in:

  • Interrupt handling: To identify which interrupt has the highest priority.
  • Data multiplexing: To select the highest priority data source.
  • Resource arbitration: To manage access to shared resources.
  • Signal compression: To reduce multiple inputs into fewer output bits.

Designing a 4-to-2 Priority Encoder Using If-Else Statements

Let’s dive into a practical example: a 4-input to 2-output priority encoder. The inputs are labeled I3 (highest priority) down to I0 (lowest priority). The output is a 2-bit binary code representing the highest active input.

Truth Table Overview

Inputs (I3 I2 I1 I0)Output (Y1 Y0)Explanation
000000Default output when no inputs active
000100I0 active
001001I1 active
010010I2 active
100011I3 active (highest priority)

Verilog Implementation Using If-Else

Here’s how you can implement this logic in Verilog:

module priority_encoder_4to2 (
    input  wire [3:0] in,
    output reg  [1:0] out
);

always @(*) begin
    if (in[3]) begin
        out = 2'b11;  // Highest priority input
    end else if (in[2]) begin
        out = 2'b10;
    end else if (in[1]) begin
        out = 2'b01;
    end else if (in[0]) begin
        out = 2'b00;
    end else begin
        out = 2'b00;  // Default output when no inputs active
    end
end

endmodule

How It Works

  • The always @(*) block ensures the output updates whenever inputs change.
  • The if-else ladder checks inputs starting from the highest priority (in[3]).
  • As soon as it finds an active input, it assigns the corresponding binary code to the output.
  • If no inputs are active, the output defaults to 00.

Alternative Approach: Using Case Statements

You can also use a casez statement with wildcards for a clean, readable implementation:

always @(*) begin
    casez (in)
        4'b1???: out = 2'b11; // I3 active
        4'b01??: out = 2'b10; // I2 active
        4'b001?: out = 2'b01; // I1 active
        4'b0001: out = 2'b00; // I0 active
        default: out = 2'b00; // No inputs active
    endcase
end

Tips for Designing Priority Encoders

  • Always start checking from the highest priority input.
  • Ensure only one output code is active at a time.
  • Use default cases to handle no-input-active scenarios.
  • For larger input sizes (e.g., 8-to-3), the same logic scales with more if-else or case branches.

Priority encoders are fundamental building blocks in digital systems, enabling efficient signal prioritization and encoding. 

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Digital Electronics, Verilog Tags:Digital Design, Interrupt handling, Priority Encoder, Resource arbitration

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