How to Design and Test a CRC Generator in Verilog Using Shift Registers and XOR

Ensuring data integrity is a critical aspect of digital communication and storage systems. One of the most reliable and widely used error-detecting techniques is the Cyclic Redundancy Check (CRC). If you’re working with FPGAs, ASICs, or digital systems, implementing a CRC generator efficiently in hardware is essential.

In this comprehensive blog post, we’ll walk you through designing a CRC generator in Verilog using shift registers and XOR operations, and provide a practical testbench to verify your design. Whether you’re a beginner or looking to refresh your knowledge, this guide covers everything you need to get started.

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What is a CRC Generator?

CRC is an error-checking code that treats data as a polynomial and divides it by a fixed generator polynomial. The remainder of this division is the CRC checksum, which helps detect accidental data corruption during transmission or storage.

How Does a CRC Generator Work in Hardware?

A CRC generator can be efficiently implemented using:

• Shift registers: To hold intermediate CRC values.
• XOR gates: To perform modulo-2 addition, simulating polynomial division.
• Generator polynomial: Defines the CRC variant and feedback taps.

The process involves shifting input data bits serially into the register, XORing bits according to the polynomial, and after all bits are processed, the register contains the CRC checksum.

Designing a CRC-4 Generator: Verilog Example

Let’s implement a CRC-4 generator using the polynomial x⁴ + x + 1, represented in binary as 10011.

module crc4_generator (
    input  wire       clk,
    input  wire       reset_n,
    input  wire       data_in,
    input  wire       data_valid,
    output reg  [3:0] crc
);

    wire feedback;

    assign feedback = crc[3] ^ data_in;  // Continuous assignment

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            crc <= 4'b0000;
        end else if (data_valid) begin
            crc[3] <= crc[2];
            crc[2] <= crc[1];
            crc[1] <= crc[0] ^ feedback;
            crc[0] <= feedback;
        end
    end

endmodule

How It Works:

• The crc register stores the current remainder.
• Each clock cycle with data_valid high processes one input bit.
• The feedback bit is the XOR of the input bit and the MSB of the CRC register.
• The register shifts left, and bits are conditionally XORed based on the polynomial.
• After all bits are processed, crc holds the checksum.

Testing the CRC Generator: Verilog Testbench

To verify the CRC generator, here’s a simple testbench that sends an 8-bit data stream serially and monitors the CRC output.

`timescale 1ns / 1ps

module tb_crc4_generator;

    reg        clk;
    reg        reset_n;
    reg        data_in;
    reg        data_valid;
    wire [3:0] crc;

    // Instantiate the CRC4 generator
    crc4_generator uut (
        .clk(clk),
        .reset_n(reset_n),
        .data_in(data_in),
        .data_valid(data_valid),
        .crc(crc)
    );

    // Clock generation: 10ns period
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    // Test stimulus
    initial begin
        // Initialize inputs
        reset_n = 0;
        data_in = 0;
        data_valid = 0;

        // Apply reset
        #20;
        reset_n = 1;

        // Send a test data sequence serially (example: 8'b11010110)
        send_bit(1);
        send_bit(1);
        send_bit(0);
        send_bit(1);
        send_bit(0);
        send_bit(1);
        send_bit(1);
        send_bit(0);

        // Wait to observe CRC output
        #50;

        // End simulation
        $finish;
    end

    // Task to send one bit with data_valid high for one clock cycle
    task send_bit(input bit_value);
        begin
            @(negedge clk);
            data_in = bit_value;
            data_valid = 1;
            @(negedge clk);
            data_valid = 0;
        end
    endtask

    // Monitor CRC output
    initial begin
        $monitor("Time=%0t | data_in=%b | data_valid=%b | CRC=%b", $time, data_in, data_valid, crc);
    end

endmodule

How This Testbench Works:

• Generates a 10 ns clock.
• Applies an active-low reset.
• Sends each bit of the test data serially with data_valid asserted.
• Monitors and prints the CRC register value at each step.
• Ends after the data sequence is processed.

Customizing Your CRC Generator

This design pattern can be adapted for:

• Different CRC polynomials (CRC-8, CRC-16, CRC-32).
• Wider input data widths.
• Different shift directions or initial CRC values.

Adjust the register size and XOR feedback taps according to your polynomial.

Why Use Shift Register with XOR for CRC?

• Hardware efficiency: Minimal logic and registers.
• Speed: One bit processed per clock cycle.
• Simplicity: Easy to understand and customize.
• Scalability: Works for various CRC standards.

Implementing a CRC generator using shift registers and XOR gates in Verilog is a classic, effective approach to error detection in digital systems. Coupled with a well-designed testbench, you can verify your design’s correctness and reliability.