How to Design a Clock Divider in Verilog?

In digital design, clocks are the heartbeat of your system. But sometimes, the clock frequency you get from your oscillator or PLL is too fast for certain parts of your design. That’s where a clock divider comes in handy. It helps you generate slower clock signals by dividing down a faster input clock.

In this blog post, we’ll explore how to model a clock divider in Verilog using counters. We’ll start with a simple divide-by-2 example and then move on to a more flexible, parameterized clock divider that can divide by any integer you choose.

What is a Clock Divider?

A clock divider takes a high-frequency clock and produces a lower-frequency clock by toggling the output signal after a specific number of input clock cycles. This is essential for timing control in many digital circuits, such as UARTs, timers, or any module that requires a slower clock.

Simple Divide-by-2 Clock Divider

The easiest clock divider divides the input clock frequency by 2 by toggling the output clock every input clock cycle. Here’s how you can implement it in Verilog:

module clock_div2 (
    input wire clk_in,
    input wire rst_n,
    output reg clk_out
);

always @(posedge clk_in or negedge rst_n) begin
    if (!rst_n) begin
        clk_out <= 0;
    end else begin
        clk_out <= ~clk_out;  // Toggle output every clock cycle
    end
end

endmodule

This simple module toggles clk_out on every rising edge of clk_in, effectively halving the clock frequency.

Parameterized Clock Divider: Divide by N

What if you want to divide the clock by a number other than 2? You can use a counter to count input clock cycles and toggle the output clock after a set number of cycles. Here’s a flexible Verilog module that lets you specify the division factor:

module clock_divider #(
    parameter N = 4  // Default divide by 4
)(
    input wire clk_in,
    input wire rst_n,
    output reg clk_out
);

reg [$clog2(N)-1:0] counter;

always @(posedge clk_in or negedge rst_n) begin
    if (!rst_n) begin
        counter <= 0;
        clk_out <= 0;
    end else begin
        if (counter == (N-1)) begin
            counter <= 0;
            clk_out <= ~clk_out;  // Toggle output clock
        end else begin
            counter <= counter + 1;
        end
    end
end

endmodule

• The output clock frequency is the input clock frequency divided by 2 × N.
• You can change the parameter N to any integer to get your desired clock division.

Why Use Clock Dividers?

• Adapt clock speed: Match clock frequency to the needs of different modules.
• Reduce power consumption: Slower clocks can save power in certain blocks.
• Timing control: Generate enable signals or timing pulses at lower frequencies.

Clock dividers are fundamental building blocks in digital systems, and modeling them in Verilog is straightforward. Starting with a simple toggle for divide-by-2, you can easily extend the design to a parameterized counter-based divider for any division factor.

Try implementing these clock dividers in your next project to gain better control over clock domains and timing!

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