Category: Xilinx

Synthesis and Functioning of Blocking and Non-Blocking Assignments.

March 20, 2016June 17, 2025 Priyadarshi No Comments

Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. The following example illustrates the Blocking Assignment Wave forms for the above exampleThe following example illustrates the Non-Blocking Assignment Wave forms for the above example…

DHD, Digital Electronics, Uncategorized, Verilog, VLSI Circuits, Xilinx

Different Coding Styles of Verilog Language

January 31, 2016June 16, 2025 vlsifacts 4 Comments

Verilog language has the capability of designing a module in several coding styles. Depending on the needs of a design, internals of each module can be defined at four level of abstractions. Irrespective of the internal abstraction level, the module would behave exactly in the similar way to the external environment. Following are the four…

DHD, Verilog, Xilinx

Power Analysis in XILINX Xpower Analyzer

August 27, 2015June 16, 2025 Priyadarshi 7 Comments

These are some simple steps which can be used to do the power analysis of a design using Xpower Analyzer which comes readily available in the ISE free web pack. ## Make sure your circuit can be synthesized. Then under the implement design option in the project navigator, Place and Route the design. ## The…

DHD, Xilinx