Mentor Graphics Corporation founded the Higher Education Program in 1985 to further the development of skilled engineers within the electronics industry. The program provides colleges and universities with leading edge design tools for classroom instruction and academic research to help…
Author: vlsifacts
Digital Design Methodologies
There are two basic types of digital design methodologies: top-down Design Methodology In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come…
Why VLSI?
“There is Plenty of Room at the Bottom“ A popular talk delivered by Richard Feynman to American Physical Society at California Institute of Technology in the year of 1959. This talk at that time could foresee the possibility of the…
Port Mapping for Module Instantiation in Verilog
Port mapping in module instantiation can be done in two different ways: In this post, we would take one example to understand both types of port mapping in detail. The above Figure shows an example for module instantiation. Figure shows module…
Module Instantiation in Verilog
A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating…
Ports in Verilog Module
Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All…
Module Definition in Verilog
A “module” is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but…
State Equivalence & Minimization Part – 2
The states which are equivalent, are redundant. Because by looking at the output, we can not even figure out in which state the machine is in. So, if there are two equivalent states then there is no point of using…
State Equivalence & Minimization Part – 1
Sometimes a state diagram constructed for a finite state machine contains redundant states, i.e. states whose function can be accomplished by other states. The number of memory elements required for the realization of a machine is directly related to the…
Circuit Design of Parity Generator
This post illustrates the circuit design of Even Parity Generator. State Machine diagram for the same Parity Generator has been shown below. Click here to realize how we reach to the following state transition diagram. Click here to learn the step…