Let's Program the Transistors
This post is about characterizing or calculating pin average toggling power for any on chip module, using SPICE simulations, Toggling power or Dynamic power is the power dissipated during the transition of any input signal from low to high or high to low. During this time certain amount of current is drawn from the supply…
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This part of the Interview Question Bank deals with the general transistor level questions asked in various VLSI companies Q1. If you connect the input of an inverter to its output where will the output gets settled? Ans. The output will settle at the logical threshold of the inverter ideally at VDD/2. Q2. The Vt…
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Setup and Hold time concept is one of the fundamental concepts that is very necessary for closing and analysing and timing margin. The analysis in digital domain, in Reg to Reg system is very popular but the root cause of Setup and Hold time is often not taken care of in the education system. This…
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Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. The following example illustrates the Blocking Assignment Wave forms for the above exampleThe following example illustrates the Non-Blocking Assignment Wave forms for the above example…
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I want to share my interview experience in Si2Chip, a design and layout based service company in Bangalore. I applied though the career section of the company and got the call for the Memory Design requirement. There were two telephonic technical rounds consisting of quality technical discussion. Most of the discussion revolved around Memory design…
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This post contains some very interesting interview questions asked by Synopsys the EDA giant in its interview. The questions are based on Verilog Synthesis and Simulation. Though I have included the answers; I would encourage the reader to experiment himself or herself and then discuss these in the forum. 1. How a latch gets inferred…
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Case and Conditional Statements are available in both VHDL and Verilog. These are considered as significant features of behavioral modelling, be it in VHDL or Verilog. Behavioral modelling provides high level abstraction so that the circuit can be designed by programming its functionality. Let’s say, we have to design a circuit that selects a particular…
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I got an Interview call from Tech Mahindra VLSI Dept, and I am sharing my Interview Experience here. The Interview was telephonic and and was about 55 minutes long. They asked for core technical questions related to HDL (Hardware Description Language) which you can answer correctly only if you have some basic work experience with…
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Hello everyone !!!This is my interview experience for the post of Trainee VLSI design at Silicon Interfaces, A software and VLSI Design centre. This post also presents my thoughts towards “What should be done to get noticed by VLSI companies“. This article would be of great assistance to those, who are vouching to make a…
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These are some simple steps which can be used to do the power analysis of a design using Xpower Analyzer which comes readily available in the ISE free web pack. ## Make sure your circuit can be synthesized. Then under the implement design option in the project navigator, Place and Route the design. ## The…