Let's Program the Transistors
This post is about characterizing or calculating pin average toggling power for any on chip module, using SPICE simulations, Toggling power or Dynamic power is the power dissipated during the transition of any input signal from low to high or high to low. During this time certain amount of current is drawn from the supply…
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If you are in VLSI industry, sometime or the other, you must have heard this term “Mont Carlo (MC)”. In this post let us understand the literal meaning of Monte Carlo simulation and its application in circuit design field. Going by the wiki definition of Monte Carlo “Monte Carlo methods are a broad class of computational…
This part of the Interview Question Bank deals with the general transistor level questions asked in various VLSI companies Q1. If you connect the input of an inverter to its output where will the output gets settled? Ans. The output will settle at the logical threshold of the inverter ideally at VDD/2. Q2. The Vt…
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Many of you might have worked on different VLSI technology nodes such as 180 nm, 90 nm, 45 nm etc. in circuit simulation tools like Cadence etc. With the invention and evolution of transistors, various technologies came into existence and more would continue to come in future. According to Moore’s law, the number of transistors…
Setup and Hold time concept is one of the fundamental concepts that is very necessary for closing and analysing and timing margin. The analysis in digital domain, in Reg to Reg system is very popular but the root cause of Setup and Hold time is often not taken care of in the education system. This…
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MOS scaling has introduced many undesired effects, known second order ones being channel length modulation, velocity saturation, mobility degradation etc. These are introducing a new set of challenges for the designers. From the performance perspective, supply voltage scaling has reduced the driving capability of MOS due to decrease in effective overdrive voltage. On the other…
Here are some examples on blocking and non-blocking assignments in Verilog, that can be really useful for the budding design Engineers. First let us discuss the features of these assignments. The following example illustrates the Blocking Assignment Wave forms for the above exampleThe following example illustrates the Non-Blocking Assignment Wave forms for the above example…
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I want to share my interview experience in Si2Chip, a design and layout based service company in Bangalore. I applied though the career section of the company and got the call for the Memory Design requirement. There were two telephonic technical rounds consisting of quality technical discussion. Most of the discussion revolved around Memory design…
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“There is Plenty of Room at the Bottom“ A popular talk delivered by Richard Feynman to American Physical Society at California Institute of Technology in the year of 1959. This talk at that time could foresee the possibility of the revolution which has been brought by VLSI today. The term VLSI stands for Very Large…
For the design of any circuit with the CMOS technology; We need parallel or series connections of nMOS and pMOS with a nMOS source tied directly or indirectly to ground and a pMOS source tied directly or indirectly to Vdd. A basic CMOS structure of any 2-input logic gate can be drawn as follows: 2…