Author: Sidhartha

Need of Fault Tolerant VLSI System Design

In recent few years VLSI design has achieved remarkable growth. High performance (peta-scale) computing is a reality now and we are expecting exa-scale computing by 2020. We talk about many core processor now a days. Intel’s Xeon Phi (Knights Landing)…

Delay in Assignment (#) in Verilog

Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment…

Digital Design Methodologies

There are two basic types of digital design methodologies: top-down design methodology bottom-up design methodology. top-down Design Methodology In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further…

Why VLSI?

“There is Plenty of Room at the Bottom“ A popular talk delivered by Richard Feynman to American Physical Society at California Institute of Technology in the year of 1959. This talk at that time could foresee the possibility of the…

Module Instantiation in Verilog

A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating…

Ports in Verilog Module

Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All…