Author: Sidhartha

Creating Resistor Layout

Create a new cell as in case of schematic earlier with the view as {layout} and with the same cell name Resistive_divider. Now under the library design_1.jelib you can find a layout cell named as Resistive_divider {lay} with an yellow indicator as…

Creating Resistor Schematic

1. Let’s create a Library Go to Explorer (beside the Components view); you will find LIBRARIES name as noname File –> Save Library As Go to the location where you want to save your design (eg: $PATH/Electric/Designs) Name the design (library…

Starting and Setting-up Electric

1. Start Electric: You will see the following window. 2. Towards the bottom of the window, you will find an Electric Messages Window where you can find different messages throughout any design. 3. You can change the background color of the window…

Getting Started with Electric

Installation Steps: Ensure Java is installed and updated on your system Download and save electric-9.07.jar to your computer (It is a java archived file) – You just have to double-click this .jar file and there you go. If java is…

Redundancy in Fault Tolerance

In the previous post we have understood the need of Fault Tolerance in VLSI System Design. A VLSI system can broadly be considered as a union of following 3 layers: Hardware Layer (Processing cores, Memories, etc.) Software Layer (OS, Program…

Delay in Assignment (#) in Verilog

Syntax: #delay It delays execution for a specific amount of time, ‘delay’. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // “expression” gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment…

Why VLSI?

“There is Plenty of Room at the Bottom“ A popular talk delivered by Richard Feynman to American Physical Society at California Institute of Technology in the year of 1959. This talk at that time could foresee the possibility of the…